sequence_item的定义以及注意事项:
1,
class packet extends uvm_sequence_item;
rand int len;
rand int crc;
function new (string name = "packet");
super.new(name);
this.crc.rand_mode(0);
endfunction
constraint len_c{
len > 0;
}
endclass
2,
import uvm_pkg::*;
class packet extends uvm_sequence_item;
uvm_cmdline_processor clp = uvm_cmdline_processor::get_inst();
string clp_arg;
rand int addr;
rand int data;
rand int len;
int len_arg;
int len_flg;
rand int crc;
function new (string name = "packet");
super.new(name);
this.crc.rand_mode(0);
if(clp.get_arg_value("+len=",this.clp_arg)) begin
this.len_arg=this.clp_arg.atoi();
this.len_flg=1;
end
endfunction
constraint addr_data_c{
addr > 16'hffff;
data > 0;
}
constraint len_c{
if(len_flg == 1){
len == len_arg;
}else {
len > 0;
}
}
endclass
所有的item必须继承uvm_sequence_item。
所有的定义为rand,但是可以通过this.crc.rand_mode(0)来关掉随机化,这里的crc就是通过其他数据生成的,不能随机化。
可以添加多个constraint 组。
constraint里边还可以根据cmdline的参数来选择不同的rand。
//A=ABSTRACT Y=PHYSICAL
//F=REFERENCE, S=SHALLOW, D=DEEP
//K=PACK, R=RECORD, P=PRINT, M=COMPARE, C=COPY
//--------------------------- AYFSD K R P M C
parameter UVM_DEFAULT = 'b000010101010101;
parameter UVM_ALL_ON = 'b000000101010101;
So, UVM_DEFAULT turns on the "D"EEP bit, whereas UVM_ALL_ON (ironically) has it turned off.
参考:
http://forums.accellera.org/topic/991-uvm-all-on-vs-uvm-default/