ISE Simulator综合后仿真 - How do you run Post Synthesis Simulation in ISE Project Navigator?

本文提供了使用ISE Design Suite在ISE Project Navigator中运行Post-Synthesis Simulation的具体指南,包括创建项目、添加模块、设置顶层模块、运行综合、生成后综合仿真模型以及在ISE Design Suite中运行仿真等步骤。
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转自:http://china.xilinx.com/support/answers/45668.htm


疑问描述

How do you run Post Synthesis Simulation in ISE Project Navigator?

解决方案

Follow these steps to run simulation:
  1. Create the project in ISE Project Navigator and add all the required modules including the testbench.
  2. Set the module (DUT) you want to perform Post-Synthesis Simulation as the Top Module.
  3. Run Synthesis.
  4. Once the design is synthesized. Expand the Synthesize -> XST option and double-click on Generate Post-Synthesis Simulation Model. This runs NetGen to create the simulation netlist. The output is placed in the "./netgen/synthesis" folder in your project directory. The file generated is named: <top_module_name>_synthesis.vhd/v. This file would be a VHDL or Verilog file depending on the source file of the synthesized module. Alternately, you can right-click on Generate Post-Synthesis Simulation Model and change the value of Simulation Model Target (VHDL/Verilog) as per your needs.
  5. In your "project" directory, create a new ".prj" file. Add the two entries as shown below:
    vhdl/verilog work (or library name) "netgen\synthesis\<top_module_name>_synthesis.vhd/v"
    vhdl/verilog work (or library name) "testbench.vhd/v"


  6. Open the ISE Design Suite Command Prompt and run the following commands (depending on simulation language):
    • Verilog: fuse -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o x_synthesis.exe -prj new.prj work.<testbench> work.glbl
    • VHDL: fuse -intstyle ise -incremental -lib unisim -lib unimacro -lib xilinxcorelib -lib secureip -o x_synthesis.exe -prj new.prj work.<testbench>


  7. Run the generated simulation executable x_synthesis.exe -gui to open ISIM GUI.
  8. The outputted waveform is the Post-Synthesis Simulation for the design under test.
适用于

设计工具

  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • ISE Design Suite - 13.4

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