模拟clk经过组合逻辑延时,生成clk_gate_delay。相异或后得到二倍频信号dpll_clk。
注:本代码为模拟的测试代码,不可综合
`timescale 1ns/1ns
module gate_delay_pll();
reg clk;
reg clk_gate_delay; //模拟经过数个逻辑门后的时钟信号(有延时)
wire dpll_clk;
assign dpll_clk = clk^clk_gate_delay;
initial begin #300; $finish(); end
initial begin
clk = 1'b0;
forever begin
clk = 1'b1;
#10;
clk = 1'b0;
#10;
end
end
initial begin
clk_gate_delay = 1'b0;
#3;
forever begin
clk_gate_delay = 1'b1;
#10;
clk_gate_delay = 1'b0;
#10;
end
end
endmodule