并发sequence
当有多个sequence在同一时刻请求sequencer发送时,那么sequencer,就会仲裁sequence发送的先后顺序
可配置sequencer的仲裁机制如下所示:
注意: 在UVM 1.2, 带这些宏“UVM_”前缀; 在 UVM 1.1,不带“UVM_“前缀.
SEQ_ARB_STRICT_FIFO仲裁模式,不锁定传输
设置仲裁模式:优先级高先出,同优先级下遵从fifo先进先出
不设置锁定传输
package pack1; //pack1头
import uvm_pkg::*; //+UVM
`include "uvm_macros.svh"//+工厂
class item extends uvm_sequence_item;
rand int data_auto;
`uvm_object_utils_begin(item)
`uvm_field_int(data_auto,UVM_ALL_ON)
`uvm_object_utils_end
function new(string name = "item");
super.new(name);
endfunction
endclass
//底层sequence
class child_seq extends uvm_sequence;
rand int database = 0;
`uvm_object_utils(child_seq)
function new(string name = "child_seq");
super.new(name);
endfunction
task body();
item req;
repeat(2) begin
`uvm_do_with(
req,
{data_auto inside {[database:database+9]};}
)
end
endtask
endclass
//顶层sequence
class top_seq extends uvm_sequence;
`uvm_object_utils(top_seq)
function new(string name = "top_seq");
super.new(name);
endfunction
task body();
child_seq cseq0,cseq1,cseq2;
m_sequencer.set_arbitration(SEQ_ARB_STRICT_FIFO);
//设置仲裁模式:优先级高先出,同
//优先级下遵从fifo先进先出
fork
`uvm_do_pri_with(cseq0,500,{database == 10;})
`uvm_do_pri_with(cseq1,500,{database == 20;})
`uvm_do_pri_with(cseq2,300,{database == 30;})
//sequence 优先级 约束
join
endtask
endclass
class seqr extends uvm_sequencer;
`uvm_component_utils(seqr)
function new(string name = "seqr", uvm_component parent = null);
super.new(name, parent);
endfunction
endclass
class dri extends uvm_driver;
`uvm_component_utils(dri)
function new(string name = "dri", uvm_component parent = null);
super.new(name, parent);
endfunction
task run_phase(uvm_phase phase);
uvm_sequence_item temp ;
item req;
forever begin
seq_item_port.get_next_item(temp);
void'($cast(req,temp));
$display("\n=================================================");
`uvm_info("driver","driver already recive item", UVM_LOW)
`uvm_info("driver",$sformatf("item in sequence:%s",req.get_parent_sequence().get_name()), UVM_LOW)
`uvm_info("data_auto",$sformatf("%d",req.data_auto), UVM_LOW)
$display("=================================================\n");
//只告诉完成,不发送响应(response)
seq_item_port.item_done();
end
endtask
endclass
class env extends uvm_env;
seqr seqr0;
dri dri0;
`uvm_component_utils(env)
function new(string name="env" ,uvm_component parent = null);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
seqr0 = seqr::type_id::create("seqr0",this);
dri0 = dri::type_id::create("dri0",this);
endfunction
function void connect_phase(uvm_phase phase);
dri0.seq_item_port.connect(seqr0.seq_item_export);
endfunction
endclass
class test1 extends uvm_test;
env env0;
`uvm_component_utils(test1)
function new(string name = "test1", uvm_component parent = null);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
env0 = env::type_id::create("env0",this);
`uvm_info("test1",$sformatf("build"), UVM_LOW)
endfunction
task run_phase(uvm_phase phase);
top_seq seq0;
phase.raise_objection(this);
`uvm_info("test1",$sformatf("run"), UVM_LOW)
seq0 = new();
seq0.start(env0.seqr0);
phase.drop_objection(this);//退出run_phase需要先落手
endtask
endclass
endpackage
//--------------------------------------module---------------------------------
module hardware1;
import pack1::*;
import uvm_pkg::*; //+UVM
initial begin
run_test("test1");
end
endmodule
这里的sequence0和sequence1有相同的优先级且高于sequence2
SEQ_ARB_STRICT_FIFO仲裁模式遵从:优先级高先出,同优先级下遵从fifo先进先出
SEQ_ARB_STRICT_FIFO仲裁模式,设置锁定传输
上锁方式分lock和greb 在sequence的body()中使用lock()…unlock()或grab()…ungrab(),
可以让在其中间发送的所有transaction连续的获取sequencer的仲裁,从而连续的发送到driver而不被别是sequence打断。
二者的区别仅在仲裁机制不一样:
lock会放在仲裁队列的末尾,sequencer将原来就在仲裁队列里的transaction发送完后才执行lock的transaction,
一旦lock占用sequencer后,只有unlock后才释放。
grab会放在仲裁队列的最前面,sequencer会立即执行grab的transaction,同样一旦grab占用sequencer后,只有ungrab后才释放。
grab实时性强,是插队操作。unlock则不是。
以上是网络的教程但是我观察到的现象不是这样的,在同一时刻,有多个sequence请求仲裁,这里面一旦有一个sequence的body正在请求上锁(无论lock还是grab),会先无视优先级的把上锁的sequence里的item全部发送出去。这里保留疑问,有可能是我个人程序问题导致错误
这段程序里共有4个sequence,0的优先级最高,1、2和3有相同的仲裁优先级,
每个sequence都发送三个item,但是这里将sequence1上锁传输,0、2和3不上锁
package pack1; //pack1头
import uvm_pkg::*; //+UVM
`include "uvm_macros.svh"//+工厂
class item extends uvm_sequence_item;
rand int data_auto;
`uvm_object_utils_begin(item)
`uvm_field_int(data_auto,UVM_ALL_ON)
`uvm_object_utils_end
function new(string name = "item");
super.new(name);
endfunction
endclass
//底层sequence
class child_seq extends uvm_sequence;
rand int database = 0;
`uvm_object_utils(child_seq)
function new(string name = "child_seq");
super.new(name);
endfunction
task body();
item req;
repeat(3) begin
`uvm_do_with(
req,
{data_auto inside {[database:database+9]};}
)
end
endtask
endclass
//上锁的sequence
class lock_seq extends uvm_sequence;
rand int database = 0;
`uvm_object_utils(lock_seq)
function new(string name = "lock_seq");
super.new(name);
endfunction
task body();
item req;
m_sequencer.lock(this);
$display("LOCKED");
repeat(3) begin
`uvm_do_with(
req,
{data_auto inside {[database:database+9]};}
)
end
m_sequencer.unlock(this);
$display("UNLOCKED");
endtask
endclass
//顶层sequence
class top_seq extends uvm_sequence;
`uvm_object_utils(top_seq)
function new(string name = "top_seq");
super.new(name);
endfunction
task body();
child_seq cseq0,cseq2,cseq3;
lock_seq cseq1;
m_sequencer.set_arbitration(SEQ_ARB_STRICT_FIFO);
//设置仲裁模式:优先级高先出,同
//优先级下遵从fifo先进先出
fork
`uvm_do_pri_with(cseq0,5,{database == 10;})
`uvm_do_pri_with(cseq1,3,{database == 20;})
`uvm_do_pri_with(cseq2,3,{database == 30;})
`uvm_do_pri_with(cseq3,3,{database == 40;})
//sequence 优先级 约束
join
endtask
endclass
class seqr extends uvm_sequencer;
`uvm_component_utils(seqr)
function new(string name = "seqr", uvm_component parent = null);
super.new(name, parent);
endfunction
endclass
class dri extends uvm_driver;
`uvm_component_utils(dri)
function new(string name = "dri", uvm_component parent = null);
super.new(name, parent);
endfunction
task run_phase(uvm_phase phase);
uvm_sequence_item temp ;
item req;
forever begin
seq_item_port.get_next_item(temp);
void'($cast(req,temp));
$display("\n=================================================");
`uvm_info("driver","driver already recive item", UVM_LOW)
`uvm_info("driver",$sformatf("item in sequence:%s",req.get_parent_sequence().get_name()), UVM_LOW)
`uvm_info("data_auto",$sformatf("%d",req.data_auto), UVM_LOW)
$display("=================================================\n");
//只告诉完成,不发送响应(response)
seq_item_port.item_done();
end
endtask
endclass
class env extends uvm_env;
seqr seqr0;
dri dri0;
`uvm_component_utils(env)
function new(string name="env" ,uvm_component parent = null);
super.new(name,parent);
endfunction
function void build_phase(uvm_phase phase);
seqr0 = seqr::type_id::create("seqr0",this);
dri0 = dri::type_id::create("dri0",this);
endfunction
function void connect_phase(uvm_phase phase);
dri0.seq_item_port.connect(seqr0.seq_item_export);
endfunction
endclass
class test1 extends uvm_test;
env env0;
`uvm_component_utils(test1)
function new(string name = "test1", uvm_component parent = null);
super.new(name, parent);
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
env0 = env::type_id::create("env0",this);
`uvm_info("test1",$sformatf("build"), UVM_LOW)
endfunction
task run_phase(uvm_phase phase);
top_seq seq0;
phase.raise_objection(this);
`uvm_info("test1",$sformatf("run"), UVM_LOW)
seq0 = new();
seq0.start(env0.seqr0);
phase.drop_objection(this);//退出run_phase需要先落手
endtask
endclass
endpackage
//--------------------------------------module---------------------------------
module hardware1;
import pack1::*;
import uvm_pkg::*; //+UVM
initial begin
run_test("test1");
end
endmodule