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SV assertion
Holden_Liu
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assertion for clock switch and clock glitch
Code sequence clk_seq(sig,real val); realtime t1,t2; @(posedge sig) (1,t1=$realtime) ##1 @(negedge sig) (1,t2=$realtime,val = t2 - t1); endsequence function automatic void calculate (real val1,val2,val3,jitter,percent,min_cycle);原创 2021-09-05 17:39:07 · 1050 阅读 · 0 评论 -
assertion for reset synchronous release
Code sequence mark_time(sig,realtime t); @(posedge sig) (1,t=$realtime); endsequence property p_rstn_sync(en,rstn,clk); realtime t1,t2; @(posedge clk) disable iff (!en) mark_time(rstn,t1) ##0 mark_time(clk,t2) |-> if(t1!=t2)原创 2021-09-05 17:14:42 · 762 阅读 · 0 评论 -
systemverilog assertion在 ##m延迟 和 [*m]连续重复 中使用变量代替常量
property Delay; @(posedge clk) trigger |-> ##delay outputendproperty##delay 只能是常量,比如##2,如果是变量编译报错。可以如下写:property delay;int number; @(posedge clk) (trigger,number=delay) ##1 (1,num...原创 2019-04-04 16:20:26 · 2959 阅读 · 2 评论 -
assertion 语句
property on2off_delay_3; @(posedge clock) disable iff (fw_clk_mode || clk_on2off_delay==10) $fell(gated_clk) -> (($past(delay_cnt),(11)) == 16'h1);endpropertyassert property(on2off_delay_3...原创 2019-07-29 18:53:12 · 1220 阅读 · 0 评论