显示译码器的设计

显示译码器的设计
1.利用QuartusⅡ完成8段数码显示译码器的Verilog硬件设计。
程序：
module DECL8S(rst_n,din,dout,en);
input [3:0]din;
input rst_n;
output reg [7:0]dout;
output en;
always@(din)
case(din)
4’b0000:dout=8’b00000011;
4’b0001:dout=8’b10011111;
4’b0010:dout=8’b00100101;
4’b0011:dout=8’b00001101;
4’b0100:dout=8’b10011001;
4’b0101:dout=8’b01001001;
4’b0110:dout=8’b01000001;
4’b0111:dout=8’b00011111;
4’b1000:dout=8’b00000001;
4’b1001:dout=8’b00001001;
4’b1010:dout=8’b00010001;
4’b1011:dout=8’b11000001;
4’b1100:dout=8’b11000001;
4’b1101:dout=8’b01111011;
4’b1110:dout=8’b01100001;
4’b1111:dout=8’b01110001;
default:dout=8’b00000000;
endcase
assign en=0;
endmodule
2.仿真报告截图