1 定义一个sequence,里面对应的寄存器配置;
class case0_cfg_vseq extends uvm_sequence;
`uvm_object_utils(case0_cfg_vseq)
`uvm_declare_p_sequencer(my_vsqr)
function new(string name= "case0_cfg_vseq");
super.new(name);
endfunction
virtual task body();
uvm_status_e status;
uvm_reg_data_t value;
if(starting_phase != null)
starting_phase.raise_objection(this);
p_sequencer.p_rm.invert.read(status, value, UVM_FRONTDOOR);
`uvm_info("case0_cfg_vseq", $sformatf("invert's initial value is %0h", value), UVM_LOW)
p_sequencer.p_rm.invert.write(status, 1, UVM_FRONTDOOR);
p_sequencer.p_rm.invert.read(status, value, UVM_FRONTDOOR);
`uvm_info("case0_cfg_vseq", $sformatf("after set, invert's value