1、generate
generate语句能够生成有规律的代码,较少语句数量,提高效率。
注意事项 :
- genevar 定义的变量 在同一个模块中不能重复使用,用i、m、n表示,否则综合会报warning
- 注意格式 genvar 变量名 ;generate for循环 begin:循环体名称 循环内容end endgenerate
2、代码实现
module data_delay
#( parameter DELAY_CNT =31 )
(
input clk ,
input rstn ,
input data_vld_in ,
input [1024-1:0] data_in ,
output data_vld_out ,
output [1024-1:0] data_out
);
wire rd_en ;
wire wr_en ;
reg [DELAY_CNT-1:0] data_vld_dly ;
assign wr_en = data_vld_in ;
assign rd_en =data_vld_dly[DELAY_CNT-2] ;
assign data_vld_out = data_vld_dly[DELAY_CNT-1] ;
genvar i ;
generate
for(i=0; i<DELAY_CNT;i=i+1) begin : data_vld_in_d
always@(posedge clk or negedge rstn)
begin
if(!rstn)
data_vld_dly [i] <= 1'b0 ;
else begin
if(i==0)
data_vld_dly [i] <= data_vld_in;
else
data_vld_dly [i] <= data_vld_dly[i-1];
end
end
endgenerate
data_delay_fifo_32x1024_wrapper data_delay_fifo_32x1024_wrapper_u0
(
.clk (clk ),
.rstn (rstn ),
.rd_data (data_out ),
.rd_en (rd_en ),
.wr_data (data_in ),
.wr_en (wr_en ),
.empty (empty_nc ),
.full (full_nc ),
.ovf_int (ovf_nc ),
.udf_int (udf_int )
);
endmodule