set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sys_clk]

在移植AX7035的ddr3读写到XME0712(相同芯片)板上时遇到
报错: (有提示约束方法)

[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sys_clk] >

input_clock (IBUFDS.O) is locked to IOB_X1Y26
inst_clock/inst/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y1

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
inst_clock/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X1Y1
and inst_clock/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31

网上的几种说法:
1、
大致的意思是:
输入的时钟驱动CMT时,如果在同一时钟区域没有MMCM/PLL,则需要设置CLOCK_DEDICATED_ROUTE = BACKBONE 约束。比如单个时钟驱动多个CMT的情况。
如果由普通的IO管脚驱动全局时钟资源,比如bufg或者mmcm,则CLOCK_DEDICATED_ROUTE = FALSE。

2、
Vivado的外部时钟输入问题:
在使用basys3进行摄像头配置的时候出现了如下问题,最后经上网查阅资料最后得以解决,出现这个问题的原因是,遇到上面的问题是因为我们将外部输入的一个时钟管脚 OV7670_PCLK(摄像头输出给FPGA的像素时钟)分配到了一个普通的IO口上面,如果是用一个专用的时钟管脚,比如说ZedBoard有专有时钟管脚 Y9就不会出现这样的错误了。
因为是IO管脚上,所以其周围没有全局时钟 BUFG,所以我们在 XDC 里使用:set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {OV7670_PCLK_IBUF}] 来屏蔽 Xilinx 的检测,从而通过编译。这个方式在软件提示的错误中也提供了解决方法,
  
3、
斜体样式这种问题是因为:
从外部来的(接到板子上的)always语句中的敏感信号为时钟以外的外部信号,因为Vivado在处理外部时钟信号的时候会自动添加BUFG模块来去除时钟的抖动,但是其他的信号就不会这样做,这样的话在always语句的敏感信号列表中使用没有去抖动的外部信号就有可能导致系统不稳定,所以会出现这个错误。
需要在IO配置文件最后添加:set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets reset_IBUF]

原文链接:https://blog.csdn.net/yundanfengqing_nuc/article/details/88236742

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Models are now part of an increasing number of engineering processes (such as software engineering). However, in most cases, they are still confined to a simple documentation role instead of being actively integrated into the engineering process. As opposed to this passive approach, the field of Model-Driven Engineering (MDE) aims to consider models as first class entities. It also considers that the different kinds of handled items (such as the tools, the repositories, etc.) can be viewed and represented as models. The model-driven approach supposes to provide model designers and developers with a set of operations dedicated to the manipulation of models. In this context, model transformation appears to be a central operation for model handling: it aims to make it possible to specify the way to produce a number of target models based on a set of source models. In the scope of the model-driven engineering, it is assumed that model transformations, as any other model-based tool, can be modelled, which means that they have to be considered themselves as models. This section aims to provide an overview of the main MDE concepts, with a particular focus on model transformation. To this end, it first presents, in Section 2.1, the organisation of the model-driven architecture. This first section addresses the model definition mechanisms that constitute the core of the MDE area: it introduces the notions of models, metamodels and metametamodels, as well as the conformance relation that relates these different artefacts. The second part of the section more particularly deals with model transformation. It provides an overview of the conceptual model transformation architecture and detailed the way this conceptual architecture is matched to the ATL language.

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