元件：四位二进制计数加法器

LIBRARY IEEE
USE IEEE.STD_LOGIC_1164.ALL;

ENTITY adder IS
	PORT(clk :IN STD_LOGIC;
	out :INOUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END adder;

LIBRARY dataio;		--库声明
USE dataio.STD_LOGIC_OPS.ALL;

ARCHITECTURE rtl OF adder IS
BEGIN
	PROCESS (clk)
	BEGIN
		IF clk ='1' AND clk EVENT THEN
		out <= To_Vector(2,To_Integer(p)+1)
	END IF
	END PROCESS;
END rtl;