目录
非阻塞赋值
定义输入为clk,a;输出为b,c;则代码为:
module non_block(clk,a,b,c);
input clk;
input a;
output reg b,c;
always @(posedge clk)
begin
b <= a;
c <= b;
end
endmodule
阻塞赋值
定义输入为clk,a;输出为b,c;则代码为:
module block(clk,a,b,c);
input clk;
input a;
output reg b,c;
always @(posedge clk)
begin
b = a;
c = b;
end
endmodule