FPGA中模为60的BCD码加法计数器

定义输入data，load，cin，clk，reset；输出为qout；则代码为：

module    count60(clk,load,cin,reset,data,cout,qout);

    input     clk,
    input    load,cin,reset;

    output    cout;
    output    [7:0] qout;

    reg    [7:0]    qout;

alwaya    @(posedge clk)
    begin
        if(reset)
            qout <= 0;       //同步复位
        else if(load)
            qout <= data;    //同步置数
        else if(cin)
            begin
                if(qout[3:0]==9)                            //低位是否为9，是则
                    begin
                        qout[3:0] <= 0;                     //回0，并判断高位是否为5
                        if(qout[7:4] == 5)
                            qout <= 0;
                        else
                            qout[7:4] <= qout[7:4] + 1'b1;   //高位不为5，则加1
                    end
                 else                                        //低位不为9，则加1
                    qout[3:0] <= qout[3:0] + 1'b1;
                    
            end
    end

assign    cout = ((qout == 8'h59)&cin)?1:0;                     //产生进位输出信号
endmodule