FPGA学习日记（3）译码器

最新推荐文章于 2024-09-14 21:53:48 发布

finiteyhy

最新推荐文章于 2024-09-14 21:53:48 发布

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分类专栏： FPGA 文章标签：八进制译码 moduledecoder input/output random测试八位输出

本文链接：https://blog.csdn.net/jsomin/article/details/126012190

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module decoder()

module decoder
(
    input   wire   in1,
    input   wire   in2,
    input   wire   in3,
    output  reg   [0:7] out
);

always@(*)
    case({in1,in2,in3})
        3'b000: out <= 8'b0000_0001;
        3'b001: out <= 8'b0000_0010;
        3'b010: out <= 8'b0000_0100;
        3'b011: out <= 8'b0000_1000;
        3'b100: out <= 8'b0001_0000;
        3'b101: out <= 8'b0010_0000;
        3'b110: out <= 8'b0100_0000;
        3'b111: out <= 8'b1000_0000;
        default:out <= 8'b0000_0001;
    endcase

endmodule

tb_decoder

`timescale 1ns/1ns
module tb_decoder();
reg in1;
reg in2;
reg in3;
wire [0:7] out;

initial
    begin
        in1 <= 2'b0;
        in2 <= 2'b0;
        in3 <= 2'b0;
    end

always #10 in1 <= {$random}%2;
always #10 in2 <= {$random}%2;
always #10 in3 <= {$random}%2;

initial 
    begin
        $timeformat(-9,0,"ns",6);
        $monitor("@time %t: in1=%b in2=%b in3=%b out=%b,$time",in1,in2,in3,out);
    end

decoder decoder_inst
(
    .in1(in1),
    .in2(in2),
    .in3(in3),
    .out(out)

);


endmodule