[vcs]file list 寫法

vcs 通過吃file list 對 bench 進行 compile，那file list有哪些需要注意的呢？（以package為例）

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1. 先寫top_define的絕對路徑，它主要包括env要用的define和macro;

2. 加入uvm library (路徑僅示範)

      +incdir+/proj/UVM/uvm/latest/src/

      +incdir+/proj/UVM/uvm/latest/src/dpi/

3. 加入design 相關的庫文件的路徑；

4. 加入rtl 的路徑；

5. 加入assertion 和bind 文件；

6. 加入ENV的文件路徑；

    +incdir+/proj/uvm_xxx_top/sim/uvm/agents/a_agent

     /proj/uvm_xxx_top/sim/uvm/agents/a_agent/a_pkg.sv

    +incdir+/proj/uvm_xxx_top/sim/uvm/env

    /proj/uvm_xxx_top/sim/uvm/env/glb_cfg_pkg.sv

     +incdir+/proj/uvm_xxx_top/sim/uvm/ral_mdl

    /proj/uvm_xxx_top/sim/uvm/ral_mdl/ral_mdl_pkg.sv

   +incdir+/proj/uvm_xxx_top/sim/uvm/vseq

   /proj/uvm_xxx_top/sim/uvm/vseq/vseq_pkg.sv 

   +incdir+/proj/uvm_xxx_top/sim/uvm/env

    /proj/uvm_xxx_top/sim/uvm/env/env_pkg.sv

  +incdir+/proj/uvm_xxx_top/sim/uvm/testcase

    /proj/uvm_xxx_top/sim/uvm/env/testcase_pkg.sv

  +incdir+/proj/uvm_xxx_top/sim/uvm/top_module

    /proj/uvm_xxx_top/sim/uvm/env/top.sv

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其中top.sv 如何寫呢？

import uvm_pkg::*;
import ral_mdl_pkg::*;
import testcase_pkg::*;
module top;

....
endmodule

agent pkg 實例：

`include "aa_if.sv"

package aa_pkg;

  import uvm_pkg::*;
  
  `include "uvm_macros.svh"
  `include "aa_trans.sv"
  `include "aa_sequencer.sv" 
  `include "aa_driver.sv"
  `include "aa_monitor.sv" 
  `include "aa_agent.sv"
  `include "aa_seq.sv"

endpackage

其中include 順序要按照從分到總的順序，例如先寫driver,monitor再寫agent;

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+incdir+directory+
Specifies the directory or directories that VCS searches for include files used in the `include compiler directive. More than one
directory may be specified when separated by the plus (+)character.

即指定文件夾，讓tool按照指定文件夾找到include的文件進行編譯。

比如文件夾dir_a中包含文件夾dir_b,dir_b中有file_c,如何写可让tool 找到file_c呢？

法一：

+incdir+dir_a

`include "dir_b/file_c"

法二：

+incdir+dir_a/dir_b

`include "file_c"

 

uvm_pkg.sv 內容如下：

`ifndef UVM_PKG_SV
`define UVM_PKG_SV

`include "uvm_macro.svh"

package uvm_pkg;

  `include "dpi/uvm_dpi.svh"
  `include "base/uvm_base.svh"
  `include "tlm1/uvm_tlm.svh"
  `include "comps/uvm_comps.svh"
  `include "seq/uvm_seq.svh"
  `include "tlm2/uvm_tlm2.svh"
  `include "reg/uvm_reg_model.svh"
endpackage

`endif

ref: https://blog.csdn.net/w40306030072/article/details/26280443