两相非交叠时钟verilogA实现

思路是利用clk_in建立20%和80%的时间作为阈值,实现非交叠

代码

`include "constants.vams"
`include "disciplines.vams"

module nonoverlapclk_1p8(clk1, clk1_d, clk1b, clk2, clk2_d, clk2b, gnd, vdd, clk_in);
output clk1;
electrical clk1;
output clk1_d;
electrical clk1_d;
output clk1b;
electrical clk1b;
output clk2;
electrical clk2;
output clk2_d;
electrical clk2_d;
output clk2b;
electrical clk2b;
inout gnd;
electrical gnd;
inout vdd;
electrical vdd;
input clk_in;
electrical clk_in;

parameter real del=10p from [0:inf);
parameter real tdel=10p from [0:inf);
parameter real tr=10p from [0:inf);
parameter real tf=10p from [0:inf);
parameter real logich=1.8 from [0:inf);
parameter real logicl=0 from [0:inf);

analog begin
V(clk2)<+transition(V(clk_in)>logich*0.8? logich:logicl,tdel,tr,tf);
V(clk1)<+transition(V(clk_in)>logich*0.2? logicl:logich,tdel,tr,tf);
V(clk2_d)<+transition(V(clk_in)>logich*0.8? logich:logicl,tdel+del,tr,tf);
V(clk1_d)<+transition(V(clk_in)>logich*0.2? logicl:logich,tdel+del,tr,tf);
V(clk2b)<+transition(V(clk_in)>logich*0.8? logicl:logich,tdel,tr,tf);
V(clk1b)<+transition(V(clk_in)>logich*0.2? logich:logicl,tdel,tr,tf);
end

endmodule

仿真结果