`timescale 1ns / 1ps
module SYS_RST_7S #(
parameter CLK_NUM = 50_000_000
)(
input clk ,
input locked ,
output rst
);
wire add_cnt;
wire end_cnt;
reg [31: 0] cnt = 0;
always @(posedge clk)begin
if(add_cnt) begin
if(end_cnt) cnt <= CLK_NUM - 1;
else cnt <= cnt +1'b1;
end
else begin
cnt <= 0;
end
end
assign add_cnt = locked;
assign end_cnt = add_cnt && cnt == CLK_NUM - 1;
reg rst_r = 1'b1;
always @(posedge clk)begin
if(locked)begin
if(end_cnt) rst_r <= 1'b0;
end
else begin
rst_r <= 1'b1;
end
end
assign rst = rst_r;
endmodule