本文详细介绍了如何在Verilog中使用$readmemh和$readmemb函数初始化内存，包括语法、函数参数、内存文件格式，并提供了多个示例。同时讨论了在Yosys和Vivado中的具体用法。
Initialize Memory in Verilog
t’s common for a simulation or firmware to need data loading into a memory array, ram, or rom. Fortunately, Verilog provides the $readmemh and $readmemb functions for this very purpose. Unfortunately, there is a dearth of good Verilog documentation online, so using them can be harder than it should be. This how to explains the syntax and provides plenty of examples, including how to do this in Yosys and Xilinx Vivado. This post was last updated in July 2021.
If you want to learn more about FPGA memory itself, see FPGA Memory Types.
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