1、50%占空比的好处
50% duty cycleclocks are beneficial when you want to clock stuff between rising andfallingedge clock domains as it balances the timing budget between both phases.Notethat moving data between both edges of the clock effectively doubles thefrequencyof the clock on those paths (with 50% duty cycle).
也即,如果用到了该时钟的上升沿和下降沿(A信号上升沿变化,B信号下降沿读取A),那么使用50%的时钟使得在这种情况下,使用两个沿工作的寄存器的建立时间和保持时间都达到最好。
2、单时钟沿情况下的占空比
(1)if you onlyuse one edge of the clock then duty cycle is mostly unimportant. 单时钟沿情况下占空比不重要。
(2)Note thoughthat the flipflops generally have a minimum-pulse-width specification, whichwill set your minimum duty cycle.但是要注意时钟的duty cycle要大于FF的最小duty cycle。
3、非50%占空比
(1)如果IP核用下降沿采样,而我们在上升沿给数据,那么非50%占空比会用点用。可以用一个大点占空比的时钟,比如70%,使得setup time好一些。
(2)如果IP核在上升沿采样,而我们在上升沿给数据,那么非50%占空比一点用也没有。如果使用双沿,这样做会使得STA非常非常复杂。(If you use both edges oftheclock, You GREATLY complicate the timing analysis by changing the duty cycle.)