数字IC设计----寻找次小值并计数

寻找在有效电平情况下，一串数据中的次小值，并将次小值出现的次数记录

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:55:42 06/14/2021 
// Design Name: 
// Module Name:    CiDaZhi 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module CiDaZhi(
	input clk,
	input rst_n,
	input [9:0] din,
	input din_vid,
	output [9:0] dout,
	output [8:0] count
    );
	 

reg [9:0] reg_Min;
reg [9:0] reg_Mid;
reg [8:0] reg_count;
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		reg_Min <= 10'd1023;
		reg_Mid <= 10'd1023;
		reg_count <= 1'b1;
	end
	else begin
		if(din_vid) begin
					if(din <= reg_Min) begin
						reg_Min <= din;
					end
					else begin
						if(din < reg_Mid) begin
							reg_Mid <= din;
							reg_count <= 1'b1;
						end
						else begin
							reg_Min <= reg_Min;
							reg_Mid <= reg_Mid;
							if(reg_Mid == din)
								reg_count <= reg_count + 1'b1;
							else
								reg_count <= reg_count;
						end
					end
		end
	end
end


reg reg_vid1;
reg reg_vid2;
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		reg_vid1 <= 1'b0;
		reg_vid2 <= 1'b0;
	end
	else begin
	reg_vid1 <= din_vid;
	reg_vid2 <= reg_vid1;
	end
end

assign vid = reg_vid2 & (~reg_vid1);


assign dout = vid?reg_Mid:10'bz;
assign count = vid?reg_count:9'd0;

endmodule

仿真代码和结果

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   21:34:07 06/14/2021
// Design Name:   CiDaZhi
// Module Name:   E:/CODE/ISE/IC_Design/LeXin/CiDaZhi/tb_CiDaZhi.v
// Project Name:  CiDaZhi
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: CiDaZhi
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_CiDaZhi;

	// Inputs
	reg clk;
	reg rst_n;
	reg [9:0] din;
	reg din_vid;

	// Outputs
	wire [9:0] dout;
	wire [8:0] count;

	// Instantiate the Unit Under Test (UUT)
	CiDaZhi uut (
		.clk(clk), 
		.rst_n(rst_n), 
		.din(din), 
		.din_vid(din_vid), 
		.dout(dout), 
		.count(count)
	);
always #5 clk = ~clk;
	initial begin
		// Initialize Inputs
		clk = 0;
		rst_n = 0;
		din = 0;
		din_vid = 0;

		// Wait 100 ns for global reset to finish
		#100 rst_n = 1;
		#100 din_vid = 1;
		#300 din_vid = 0;
	end
	initial begin
		#200 din = 10'd1;
		#10 din = 10'd10;
		#10 din = 10'd11;
		#10 din = 10'd21;
		#10 din = 10'd4;
		#10 din = 10'd11;
		#10 din = 10'd1;
		#10 din = 10'd4;
		#10 din = 10'd11;	
		#10 din = 10'd10;
		#10 din = 10'd7;
		#10 din = 10'd8;
		#10 din = 10'd4;
		#10 din = 10'd5;
		#10 din = 10'd10;		
	end
      
endmodule

结果