FPGA调式出现的错误

1、时钟没有连上出现的错误
Error (15465): WYSIWYG primitive "ddr_avl_bridge:ddr_avl_bridge_i|wrfifo_for_sdram:wrfifo3_for_sdram_inst|wrfifo_for_sdram_fifo_161_jyih4oa:fifo_0|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_g852:auto_generated|altsyncram_gl91:fifo_ram|ram_block5a6" has clk0 port that must be connected

解决方法;从顶层一直往底层找，看看哪里的时钟没有接上。

2、DDR4的IP核没有重新genetate
Error (16383): Silicon revision parameter for the following EMIF/PHYLite atoms do not match the silicon revision of the currently selected device (20nm2). Regenerate the IP cores using the current device (10AX027H4F34E3SG).

重新打开qsys，然后重新generate就好了。