Xilinx FPGA:vivado状态机实现序列检测

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于 2024-06-11 21:00:37 发布

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本文链接：https://blog.csdn.net/loveyousosad/article/details/139608622

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一、项目内容：检测序列10010

`timescale 1ns / 1ps
///序列检测"10010"
module test_XL(
    input           sysclk              ,
    input           rst_n               ,
    input           din                 ,
    output  reg     vaild1              ,
//    output  wire    vaild2
    );
/moore
localparam          IDLE    = 3'd0;
localparam          D_1     = 3'd1;
localparam          D_10    = 3'd3;
localparam          D_100   = 3'd4;
localparam          D_1001  = 3'd5;
localparam          D_10010 = 3'd6;
reg     [2:0]       cur_state,next_state;
//ate1
always@(posedge sysclk)
    if(!rst_n)
        cur_state <= IDLE;
    else
        cur_state <= next_state;
//ate2
always@(*)
    case(cur_state)
        IDLE    :begin
            if(din == 1)
                next_state = D_1;
            else
                next_state = cur_state;
        end
        D_1     :begin
            if(din == 0)
                next_state = D_10;
            else
                next_state = cur_state;
        end
        D_10    :begin
            if(din == 0)
                next_state = D_100;
            else
                next_state = D_1;
        end
        D_100   :begin
            if(din == 1)
                next_state = D_1001;
            else
                next_state = IDLE;
        end
        D_1001  :begin
            if(din == 0)
                next_state = D_10010;
            else
                next_state = D_1;
        end
        D_10010 :begin
            if(din == 1)
                next_state = D_1;
            else
                next_state = D_100;  重复检测
//                next_state = IDLE;  非重复检测
        end   
        default:;    
    endcase
//ate3
always@(posedge sysclk)
    if(!rst_n)
        vaild1 <= 0;
    else
        case(cur_state)
             IDLE   : vaild1 <= 0;    
             D_1    : vaild1 <= 0;
             D_10   : vaild1 <= 0;
             D_100  : vaild1 <= 0;
             D_1001 : vaild1 <= 0;
             D_10010: vaild1 <= 1;
             default:;
        endcase  
//reg     [4:0]      data_reg        ;  ///10010
//always@(posedge sysclk)
//    if(!rst_n)
//        data_reg <= 0;
//    else
//        data_reg <= {din,data_reg[4:1]};    
//assign  vaild2 = (data_reg == 5'b10010) ? 1 : 0; 
endmodule