HDLBits自学笔记1:Getting Started + Verilog language.Basic

Getting Started

输出1

module top_module(
    output one
);
    assign one = 1'b1;
endmodule

Output Zero

输出0

module top_module(
    output zero
);
	assign zero = 1'b0;
endmodule

Simple wire

建立一个模块将out和in连线

module top_module( input in, output out );
	assign out = in;
endmodule

Four wires

建立一个三输入四输出模块，其连线如下：

a -> w
b -> x
b -> y
c -> z

module top_module( 
    input a,b,c,
    output w,x,y,z
);
    assign {w,x,y,z} = {a,b,b,c};
endmodule

Inverter

建立一个模块实现非门

module top_module( 
    input  in,
    output out
);
	assign out = ~in;
endmodule

AND gate

建立一个模块实现与门

module top_module( 
    input a, 
    input b, 
    output out );
	assign out = a & b;
endmodule

NOR gate

建立一个模块实现或非门

module top_module( 
    input a, 
    input b, 
    output out
);
    assign out = ~(a | b);
endmodule

XNOR gate

建立一个模块实现同或门

module top_module( 
    input a, 
    input b, 
    output out 
);
	assign out = a ~^ b;
endmodule

Declaring wires

实现如下电路：

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n
); 
    wire w1 = a & b;
    wire w2 = c & d;
    assign out = w1 | w2;
    assign out_n = ~out;
endmodule

7458 chip

实现7458芯片：

module top_module ( 
    input  p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input  p2a, p2b, p2c, p2d,
    output p2y 
);
    assign p1y = (p1a & p1b & p1c) | (p1d & p1e & p1f);
    assign p2y = (p2a & p2b) | (p2c & p2d);
endmodule