解决vivado生成bit出现约束错误的办法

本人用viva'do2019.1进行项目开发工作时(ku085),在添加了部分输出io约束时,生成bit出错。现象为:

When generating a bitstream, the following error messages occur:

ERROR: [Drc 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 3 out of 3 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. Problem ports: clk, din, dout.

ERROR: [Drc 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 3 out of 3 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. Problem ports: clk, din, dou

解决办法为:

在xdc约束文件中添加如下图的两句语句,忽视该编译映射错误(前提你的xdc约束按照原理图约束没有错误):

问题解决。

供大家开发时参考。

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