使用IP核和存储器位扩展技术设计存储器
用记事本创建 4 个文件,分别是 ram16x2-1.coe,ram16x2-2.coe, ram16x2-3.coe,ram16x2-4.coe。内容相同,均为:
memory_initialization_radix = 2;
memory_initialization_vector =
00,
00,
00,
00,
00,
00,
00,
00,
00,
00,
00,
00,
00,
00,
00,
00,
创建一个 Verilog 文件 ram16X8.v
其端口定义如下:
module ram16x8(
input clk, //时钟信号
input we, //写使能
input en, //使能信号
input [3:0] addr, // 地址线
input [7:0] datain, // 输入数据线
output [7:0] dataout // 输出数据线
);
module ram16x8_sim( ); //input
reg clk = 0;
reg en = 0;
reg we = 0;
reg [3:0] addr = 4'b0000;
reg [7:0] din = 8'h00; //output
wire [7:0] dout;
//instantiate the Unit under test
ram16x8 ut(
.clk(clk),
.we(we),
.en(en),
.addr(addr),
.datain(din),
.dataout(dout)
);
initial begin
#100 begin we = 1;en = 1; addr = 4'b0011;
din = 8'b10101010; end;
#100 begin addr = 4'b0100; din = 8'b01010101; end;
#100 begin addr = 4'b0101; din = 8'b10100101; end;
#100 begin addr = 4'b0110; din = 8'b01011010; end;
#100 begin we = 0; en = 0; addr = 4'b0011; end;
#100 addr = 4'b0100;
#100 addr = 4'b0101;
#100 addr = 4'b0110;
#100 en = 1;
#100 addr = 4'b0011;
#100 addr = 4'b0100;
#100 addr = 4'b0101;
#100 addr = 4'b0110;
#100 addr = 4'b0000;
#100 begin en = 0;
addr = 4'b0100;
end;
end always #5 clk = ~clk;
endmodule
使用IP核和存储器字扩展技术设计存储器
在 ram64x8 文件夹下,用记事本创建 4 个文件,分别是 ram16x8-1.coe,ram16x8-2.coe, ram16x8-3.coe,ram16x8-4.coe。内容相同,均为:
memory_initialization_radix = 16;
memory_initialization_vector = 00,
00,
00,
00,
00,
00,
00,
00,
00,
00,
00,
00,
00,
00,
00,
00;
创建一个 Verilog 文件 ram64X8.v 其端口定义如下:
module ram64x8(
input clk, //时钟信号
input en, //使能信号
input we, //写信号
input [5:0] addr, //地址信号
input [7:0] din, //输入信号
output reg [7:0] dout //输出信号
);
采用以下仿真程序进仿真。
module ram64x8_sim( ); //input
reg clk = 0;
reg en = 0;
reg we = 0;
reg [5:0] addr = 6'd0;
reg [7:0] din = 8'h00; //output
wire [7:0] dout;
//instantiate the Unit under test
ram64x8 ut(
.clk(clk),
.we(we),
.en(en),
.addr(addr),
.din(din),
.dout(dout)
);
initial begin
#100 begin we = 1;en = 1; addr = 6'd10; din = 8'b10101010; end;
#100 begin addr = 6'd20; din = 8'b01010101; end;
#100 begin addr = 6'd40; din = 8'b10100101; end;
#100 begin addr = 6'd60; din = 8'b01011010; end;
#100 begin we = 0; en = 0; addr = 6'd10; end;
#100 addr = 6'd20;
#100 addr = 6'd40;
#100 addr = 6'd60;
#100 en = 1;
#100 addr = 6'd10;
#100 addr = 6'd20;
#100 addr = 6'd40;
#100 addr = 6'd60;
#100 addr = 6'd0;
#100 begin en = 0;
addr = 6'd20;
end;
end always #5 clk = ~clk;
endmodule