Verilog练习(1)——ram读写测试

1、明确设计目标，是要将64个八位信号写到ram中，然后倒序读出

2、测试代码主要分三块：ram模块、ram读写模块、TB文件

//一个ram
module ip_ram(
	input clk,
	input en,
	input wr_en,
	input [5:0] addr,
	input [7:0] data,
	output reg [7:0] q
);
 
reg [7:0] ram[63:0];
 
always@(posedge clk)begin		//write to ram
	if(wr_en & en)begin
		ram[addr]<=data;
	end
end
 
always@(posedge clk)begin		//read from ram
	if(!wr_en & en)begin
		q<=ram[addr];
	end
	else begin
		q<=8'hxx;		
	end
end
endmodule
 

//ram读写控制
module ram(
	input clk,
	input rst_n
);

wire en;
wire wr_en;
wire re_en;

reg [5:0] we_addr;
reg [7:0] wr_data;
wire [7:0] re_data;
reg [6:0] cnt;

assign wr_en=(cnt>=7'd0) && (cnt<=7'd63)? 1'b1:1'b0;		//decide what en
assign re_en=(cnt>=7'd64) && (cnt<=7'd127)? 1'b1:1'b0;
assign en=wr_en | re_en;

always@(posedge clk or negedge rst_n)begin	//through cnt to decide wr or re
	if(!rst_n)
		cnt<=7'd0;
	else if(cnt==7'd127)
		cnt<=7'd0;
	else cnt<=cnt+1'b1;
end

always@(posedge clk or negedge rst_n)begin	//wr data to ram
	if(!rst_n)
		wr_data<=8'd0;
	else if(wr_en & en)
		wr_data<=wr_data+1'b1;
	else wr_data<=8'd0;
end

always@(posedge clk or negedge rst_n)begin	//we_addr to decide write or read where
	if(!rst_n)
		we_addr<=6'd0;
	else if(wr_en & en)begin
		if(we_addr==6'd63)
			we_addr<=6'd63;
		else we_addr<=we_addr+1'b1;
	end
	else if(re_en & en)begin
		we_addr<=we_addr-1'b1;
	end
end

ip_ram	u_ip_ram(
	.clk	(clk),
	.en	(en),
	.wr_en	(wr_en),
	.addr		(we_addr),
	.data		(wr_data),
	.q			(re_data)
);
endmodule

//tb测试文件
`timescale 1ns/1ps

module tb();

reg clk;
reg rst_n;

initial begin
	clk=1'b0;
	rst_n=1'b0;
	#50
	rst_n=1'b1;
end

always #10 clk=~clk;

ram u_ram(
	.clk	(clk),
	.rst_n	(rst_n)
);

endmodule

3、综合出来的电路图如下


4、modelsim测试结果