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CLOCK GATING设计3分频电路（可根据counter自定义分频）

Verilog

module GATE(
input clk_src,
input en_in,
output reg enable,
output gated_clk
);
reg clkEn;
reg [1:0]counter;

always @(posedge clk_src) begin
if(~en_in)begin
counter <= 5’b0;
enable <= 1’b0;end
else if( counter <2’d2)begin
counter <= counter + 1’b1;
enable <= 1’b0;end
else if(counter == 3’d2)begin
counter <= 3’b0;
enable <= 1’b1;end
end

always @ (clk_src or enable) begin

if ( ! clk_src)

  clkEn <= enable;

end

assign gated_clk = clkEn & clk_src;

endmodule

testbench

include "gating.v" timescale 1ns / 1ps

module tb_GATE;

// GATE Parameters
parameter PERIOD = 10;

// GATE Inputs
reg clk_src = 0 ;
reg en_in = 0 ;

// GATE Outputs
wire enable ;
wire gated_clk ;

initial
begin
forever #(PERIOD/2) clk_src=~clk_src;
end

initial
begin
#(PERIOD*2) en_in = 1;
end

GATE u_GATE (
.clk_src ( clk_src ),
.en_in ( en_in ),

.enable                  ( enable      ),
.gated_clk               ( gated_clk   )

);

initial
begin
$dumpfile(“fp.vcd”);
$dumpvars;
#1000
$finish;
end

endmodule