同步FIFO设计

同步FIFO设计

`timescale 1ns/1ns
/**********************************RAM************************************/
module dual_port_RAM #(parameter DEPTH = 16,
					   parameter WIDTH = 8)(
	 input wclk
	,input wenc
	,input [$clog2(DEPTH)-1:0] waddr  //深度对2取对数，得到地址的位宽。
	,input [WIDTH-1:0] wdata      	//数据写入
	,input rclk
	,input renc
	,input [$clog2(DEPTH)-1:0] raddr  //深度对2取对数，得到地址的位宽。
	,output reg [WIDTH-1:0] rdata 		//数据输出
);

reg [WIDTH-1:0] RAM_MEM [0:DEPTH-1];

always @(posedge wclk) begin
	if(wenc)
		RAM_MEM[waddr] <= wdata;
end 

always @(posedge rclk) begin
	if(renc)
		rdata <= RAM_MEM[raddr];
end 


endmodule  

/**********************************SFIFO************************************/
module sfifo#(
	parameter	WIDTH = 8,
	parameter 	DEPTH = 16
)(
	input 					clk		, 
	input 					rst_n	,
	input 					winc	,
	input 			 		rinc	,
	input 		[WIDTH-1:0]	wdata	,

	output reg				wfull	,
	output reg				rempty	,
	output wire [WIDTH-1:0]	rdata
);
	parameter PTR_WIDTH = $clog2(DEPTH)+ 1;
	reg [PTR_WIDTH-1:0] wr_ptr;
	reg [PTR_WIDTH-1:0] rd_ptr;

	always@(posedge clk or negedge rst_n)
		if(!rst_n)
			wr_ptr <= 'd0;
		else if(winc && !wfull)
			wr_ptr <= wr_ptr + 1'b1;
		
	always@(posedge clk or negedge rst_n)
		if(!rst_n)
			rd_ptr <= 'd0;
		else if(rinc && !rempty)
			rd_ptr <= rd_ptr + 1'b1;

	
	always@(posedge clk or negedge rst_n)
		if(!rst_n)
			wfull <= 0;
		else if((wr_ptr[PTR_WIDTH-1] ^ rd_ptr[PTR_WIDTH-1])
					&& (wr_ptr[PTR_WIDTH-2:0]==rd_ptr[PTR_WIDTH-2:0]))
			wfull <= 1;
		else
			wfull <= 0;
		
	always@(posedge clk or negedge rst_n)
		if(!rst_n)
			rempty <= 0;
		else if(wr_ptr==rd_ptr)
			rempty <= 1;
		else
			rempty <= 0;

	wire[$clog2(DEPTH)-1:0] wadd;
	wire[$clog2(DEPTH)-1:0] radd;
	wire wen;
	wire ren;

	assign wadd = wr_ptr[PTR_WIDTH-2:0];
	assign radd = rd_ptr[PTR_WIDTH-2:0];
	
	assign wen = (winc && !wfull) ;
	assign ren = (rinc && !rempty);


	dual_port_RAM #(.DEPTH(DEPTH),
					.WIDTH (WIDTH)
	) 
	dual_port_RAM (
		.wclk(clk),
		.wenc(wen),
		.waddr(wadd),
		.wdata(wdata),
		.rclk(clk),
		.renc(ren),
		.raddr(radd),
		.rdata(rdata)
	);


endmodule
``