vivado综合常见报错（持续更新）

[Synth 8-434] mixed level sensitive and edge triggered event controls are not supported for synthesis

错误原因:
一个触发器不能同时是边缘触发和电平触发的，因此不可被综合。所以最好统一，上图的情况可以去掉negedge。

IMPLEMENTATION报错

[Place 30-675] Sub-optimal placement for a global clock-capable IO pin and BUFG pair.If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets rst_IBUF_inst/O] >
rst_IBUF_inst/IBUFCTRL_INST (IBUFCTRL.O) is locked to IOB_X0Y4
rst_IBUF_BUFG_inst (BUFGCE.I) is provisionally placed by clockplacer on BUFGCE_HDIO_X0Y8
The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.
Clock Rule: rule_bufgce_bufg_conflict
Status: PASS
Rule Description: Only one of the 2 available sites (BUFGCE or BUFGCE_DIV/BUFGCTRL) in a pair can be
used at the same time
and rst_IBUF_BUFG_inst (BUFGCE.O) is provisionally placed by clockplacer on BUFGCE_HDIO_X0Y8

错误地把rst当做了时钟口，提示它需要接到时钟专用引脚。
解决方法：

1. 加入以下语句，但只是让编译器绕过这个报错，会把rst当做时钟口布局布线，可能引入时序问题。
   set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets rst_IBUF_inst/O]
2. 加一级时钟产生IP，用locked信号作为之后模块的rst信号。

[Vivado 12-106] *** Exception: java.lang.NullPointerException (See C:/Users/optiplex/AppData/Roaming/Xilinx/Vivado/vivado_pid91300.debug)

解决方法：在xilixn论坛看到，重启工程。试了一下确实不报错了