【Verilog】HDLBits之FSM（二）

一：Fsm3onehot（独热码）

The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following one-hot state encoding: A=4’b0001, B=4’b0010, C=4’b0100, D=4’b1000.
Derive state transition and output logic equations by inspection assuming a one-hot encoding. Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. (The testbench will test with non-one hot inputs to make sure you’re not trying to do something more complicated).

What does “derive equations by inspection” mean?
One-hot state machine encoding guarantees that exactly one state bit is 1. This means that it is possible to determine whether the state machine is in a particular state by examining only one state bit, not all state bits. This leads to simple logic equations for the state transitions by examining the incoming edges for each state in the state transition diagram.
For example, in the above state machine, how can the state machine can reach state A? It must use one of the two incoming edges: “Currently in state A and in=0” or “Currently in state C and in = 0”. Due to the one-hot encoding, the logic equation to test for “currently in state A” is simply the state bit for state A. This leads to the final logic equation for the next state of state bit A: next_state[0] = state[0]&(~in) | state[2]&(~in). The one-hot encoding guarantees that at most one clause (product term) will be “active” at a time, so the clauses can just be ORed together.
When an exercise asks for state transition equations “by inspection”, use this particular method. The judge will test with non-one-hot inputs to ensure your logic equations follow this method, rather that doing something else (such as resetting the FSM) for illegal (non-one-hot) combinations of the state bits.
Although knowing this algorithm isn’t necessary for RTL-level design (the logic synthesizer handles this), it is illustrative of why one-hot FSMs often have simpler logic (at the expense of more state bit storage), and this topic frequently shows up on exams in digital logic courses.

module fsm_one(
input in,
input [3:0] state,
output [3:0] next_state,
output out
);

parameter A=0,B=1,C=2,D=3;

assign next_state[A] = state[A] & ~in | state[C] & ~in;
assign next_state[B] = state[A] & in | state[B] & in | state[D] & in;
assign next_state[C] = state[B] & ~in | state[D] & ~in;
assign next_state[D] = state[C] & in;

assign out = state[D];

endmodule

二：ece241 2013 q4

Also include an active-high synchronous reset that resets the state machine to a state equivalent to if the water level had been low for a long time (no sensors asserted, and all four outputs asserted).
巩固一下英语，浅浅翻译一下。
水量一共分为四个等级，s1以下，s1和s2之间，s3和s2之间，s3以上。

• 要使水位在s1下时，fr1,fr2,fr3放水
• 要使 水位在s1和s2之间时，fr1,fr2放水
• 要使 水位在s2和s3之间时，fr1放水
• 要使水位在s3以上时，不放水
  如果之前的水位高于当前的水位，那么说明水流的流速是通过补给流水口，增加了流速，水流的太快了，需要减慢
  反之，需要加快。

module top_module (
    input clk,
    input reset,
    input [3:1] s,
    output fr3,
    output fr2,
    output fr1,
    output dfr
); 
    
    parameter IDLE = 3'd0, SENSOR_1 = 3'd1;
    parameter SENSOR_2 = 3'd2, SENSOR_3 = 3'd3;
    reg	[2:0]	current_state;
    reg [2:0]	next_state;
    
    always@(posedge clk)begin
        if(reset)begin
            current_state <= 'd0;
        end
        else begin
            current_state <= next_state;
        end
    end
    
    always@(*)begin
        case(current_state)
            IDLE:begin
                case(s)
                    3'b001:begin
                        next_state = SENSOR_1;
                    end
                    3'b011:begin
                        next_state = SENSOR_2;
                    end
                    3'b111:begin
                        next_state = SENSOR_3;
                    end
                    default:begin
                        next_state = IDLE;
                    end
                endcase
            end
            SENSOR_1:begin
                case(s)
                    3'b001:begin
                        next_state = SENSOR_1;
                    end
                    3'b011:begin
                        next_state = SENSOR_2;
                    end
                    3'b111:begin
                        next_state = SENSOR_3;
                    end
                    default:begin
                        next_state = IDLE;
                    end
                endcase
            end
            SENSOR_2:begin
                case(s)
                    3'b001:begin
                        next_state = SENSOR_1;
                    end
                    3'b011:begin
                        next_state = SENSOR_2;
                    end
                    3'b111:begin
                        next_state = SENSOR_3;
                    end
                    default:begin
                        next_state = IDLE;
                    end
                endcase
            end
            SENSOR_3:begin
                case(s)
                    3'b001:begin
                        next_state = SENSOR_1;
                    end
                    3'b011:begin
                        next_state = SENSOR_2;
                    end
                    3'b111:begin
                        next_state = SENSOR_3;
                    end
                    default:begin
                        next_state = IDLE;
                    end
                endcase
            end
            default:begin
                next_state = IDLE;
            end
        endcase
    end
    
    assign fr3 = (current_state == IDLE);
    assign fr2 = (current_state == IDLE || current_state == SENSOR_1);
    assign fr1 = (current_state == IDLE || current_state == SENSOR_1 || current_state == SENSOR_2);
    
    reg fr3_reg;
    reg fr2_reg;
    reg fr1_reg;
    always@(posedge clk)begin
        fr3_reg <= fr3;
    end
    always@(posedge clk)begin
        fr2_reg <= fr2;
    end
    always@(posedge clk)begin
        fr1_reg <= fr1;
    end
    
    always@(*)begin
        if(~fr3 & fr3_reg | ~fr2 & fr2_reg | ~fr1 & fr1_reg)begin
        	dfr = 1'b0;
    	end
        else if(fr3 & ~fr3_reg | fr2 & ~fr2_reg | fr1 & ~fr1_reg)begin
            dfr = 1'b1;
        end
    end  
    
endmodule