【Verilog】HDLBits之FSM（一）

写自己动手写cpu时写到除法器部分感觉对状态机还不是比较熟悉，做题家还是要多刷题巩固，少动脑子多花时间。

一： FSM1（异步复位）

This is a Moore state machine with two states, one input, and one output. Implement this state machine. Notice that the reset state is B.
This exercise is the same as fsm1s, but using asynchronous reset.

/*This is a Moore state machine with two states, one input, and one output. 
Implement this state machine. Notice that the reset state is B.*/
module fsm1(
input clk,
input areset,
input in,
output out
);
parameter A=1'b0,B=1'b1;//一共两个状态
reg state,next_state;
//两段式

	/*always @ (posedge clk,posedge areset)begin
		if(areset)begin
			state <= B;
		end
		else begin
			state <= nextstate;
		end
	end*/

always @ (*) begin
	case(state)
		B:begin
			if(in == 1'b1)begin
				next_state <= B;
			end
			else begin
				next_state <= A;
			end
		end
		A:begin
			if(in == 1'b1)begin
				next_state <= A;
			end
			else begin
				next_state <= B;
			end
		//end
			//default:begin
            //end
		
        end
	endcase
end
    
always @ (posedge clk,posedge areset)begin
		if(areset)begin
			state <= B;
		end
		else begin
			state <= next_state;
		end
	end
    
always @ (*) begin
	if(state == B)begin
		out = 1'b1;
	end
	else begin
		out = 1'b0;
	end
end
endmodule

二：FSM2（异步复位）

This is a Moore state machine with two states, two inputs, and one output. Implement this state machine.
This exercise is the same as fsm2s, but using asynchronous reset.

module fsm2(
input clk,
input areset,
input j,
input k,
output out
);
parameter OFF=0,ON=1;
reg state,next_state;

always @ (posedge clk,posedge areset) begin
    if(areset) begin
	state <= OFF;
end
else begin
	state <= next_state;
end
end

always @ (*) begin
	case(state)
		OFF:begin
			if(j == 0)begin
				next_state <= OFF;
			end
			else begin
				next_state <= ON;
			end
		end
		ON:begin
			if(k == 0)begin
				next_state <= ON;
			end
			else begin
				next_state <= OFF;
			end
		end
	endcase
end

always @ (*) begin
	if(state == OFF)begin
		out <= 1'b0;
	end
	else begin
		out <= 1'b1;
	end
end

endmodule	

同步复位将areset改成reset即可

三：Fsm3comb

The following is the state transition table for a Moore state machine with one input, one output, and four states. Use the following state encoding: A=2’b00, B=2’b01, C=2’b10, D=2’b11.
Implement only the state transition logic and output logic (the combinational logic portion) for this state machine. Given the current state (state), compute the next_state and output (out) based on the state transition table.

上图是状态转移表

module fsm3comb(
 input in,
    input [1:0] state,
    output [1:0] next_state,
    output out); //

    parameter A=0, B=1, C=2, D=3;

   // reg state[1:0];
    //reg next_state[1:0];

always @ (*) begin
	case(state)
		A:begin
			if(in == 1'b0)begin
				next_state <= A;
			end
			else begin
				next_state <= B;
			end
		end
		B:begin
			if(in == 1'b0)begin
				next_state <= C;
			end
			else begin
				next_state <= B;
			end
		end
		C:begin
			if(in == 1'b0)begin
				next_state <= A;
			end
			else begin
				next_state <= D;
			end
		end
		D:begin
			if(in == 0)begin
				next_state <= C;
			end
			else begin
				next_state <= B;
			end
		end
	endcase
end

always @ (*) begin
	if(state == A)begin
		out = 0;
	end else if(state == B)begin
		out = 0;
	end else if(state == C)begin
		out = 0;
	end else begin
		out = 1;
	end
end

endmodule