HDLbits算术移位寄存器

 

module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q); 
    
    integer i;
    always@(posedge clk)
        begin
            if(load)
                begin
                   q <= data; 
                end
            else if(amount == 2'b00 && ena)//算术左移1位（算术左移和逻辑左移一样）
                begin
                    q[0] <= 0;
                    for(i=0;i<=62;i=i+1)
                        q[i+1] <= q[i];
                end
            else if(amount == 2'b01 && ena)//算术左移8位
                begin
                    q[7:0] <= 8'b0;
                    for(i=0;i<=55;i=i+1)
                        q[i+8] <= q[i];
                end
            else if(amount == 2'b10 && ena)//算术右移一位
                begin
                    //q[62] <= q[63];
                    for(i=0;i<=62;i=i+1)
                        q[i] <= q[i+1];
                end
            else if(amount == 2'b11 && ena)//算术右移8位
                begin
                    q[62:55] <= {8{q[63]}};
                    for(i=0;i<=54;i=i+1)
                        q[i] <= q[i+8];
                end
            else
                 q <= q;
        end

endmodule