「HDLBits题解」Basic Gates

本专栏的目的是分享可以通过HDLBits仿真的Verilog代码 以提供参考 各位可同时参考我的代码和官方题解代码 或许会有所收益

---

题目链接：Exams/m2014 q4h - HDLBits

module top_module (
    input in,
    output out);
	assign out = in ;
endmodule

---

题目链接：Exams/m2014 q4i - HDLBits

module top_module (
    output out);
	assign out = 0 ;
endmodule

---

题目链接：Exams/m2014 q4e - HDLBits

module top_module (
    input in1,
    input in2,
    output out);
    assign out = ~ (in1 | in2) ;
endmodule

---

题目链接：Exams/m2014 q4f - HDLBits

module top_module (
    input in1,
    input in2,
    output out);
    assign out = in1 & ~in2 ;
endmodule

---

题目链接：Exams/m2014 q4g - HDLBits

module top_module (
    input in1,
    input in2,
    input in3,
    output out);
	wire t ; 
    assign t = ~(in1 ^ in2) ; 
    assign out = t ^ in3 ; 
endmodule

---

题目链接：Gates - HDLBits

module top_module( 
    input a, b,
    output out_and,
    output out_or,
    output out_xor,
    output out_nand,
    output out_nor,
    output out_xnor,
    output out_anotb
);
    assign out_and = a & b; 
    assign out_or = a | b;
    assign out_xor = a ^ b ; 
    assign out_nand = ~(a & b) ; 
    assign out_nor = ~(a | b) ; 
    assign out_xnor = ~(a ^ b) ; 
    assign out_anotb = a & ~b ; 

endmodule

---

题目链接：7420 - HDLBits

module top_module ( 
    input p1a, p1b, p1c, p1d,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
	
    assign p1y = ~(p1a & p1b & p1c & p1d) ;
    assign p2y = ~(p2a & p2b & p2c & p2d) ;

endmodule

---

题目链接：Truthtable1 - HDLBits

module top_module( 
    input x3,
    input x2,
    input x1,  // three inputs
    output reg f   // one output
);
    always @(*) begin
        f = 0 ; 
        if ((!x3 && x2 && !x1) || (!x3 && x2 && x1) || (x3 && !x2 && x1) || (x3 && x2 && x1)) 
            f = 1 ;
    end

endmodule

---

题目链接：Mt2015 eq2 - HDLBits

module top_module ( input [1:0] A, input [1:0] B, output z ); 
	assign z = A == B ? 1 : 0 ;
endmodule

---

题目链接：Mt2015 q4a - HDLBits

module top_module (input x, input y, output z);
    assign z = (x ^ y) & x ;
endmodule

---

题目链接：Mt2015 q4b - HDLBits

module top_module ( input x, input y, output z );
    assign z = ~(x ^ y) ;
endmodule

---

题目链接：Mt2015 q4 - HDLBits

module top_module (input x, input y, output z);

    wire z1, z2, z3, z4 ; 

    circuit1 IA1(x, y, z1) ; 
    circuit2 IB1(x, y, z2) ; 
    circuit1 IA2(x, y, z3) ;
    circuit2 IB2(x, y, z4) ; 

    assign z = (z1 | z2) ^ (z3 & z4) ;

endmodule

module circuit1 (
    input a, 
    input b, 
    output c 
);
    assign c = (a ^ b) & a ;
endmodule 

module circuit2(
    input a, 
    input b,
    output c
);
    assign c = ~(a ^ b) ;
endmodule 

---

题目链接：Ringer - HDLBits

module top_module (
    input ring,
    input vibrate_mode,
    output ringer,       // Make sound
    output motor         // Vibrate
);
    assign motor = vibrate_mode ? (ring ? 1 : 0) : 0 ;
    assign ringer = !vibrate_mode ? (ring ? 1 : 0) : 0 ; 

endmodule

---

题目链接：Thermostat - HDLBits

module top_module (
    input too_cold,
    input too_hot,
    input mode,
    input fan_on,
    output heater,
    output aircon,
    output fan
); 

    assign heater = mode ? (too_cold ? 1 : 0) : 0 ; 
    assign aircon = !mode ? (too_hot ? 1 : 0) : 0 ; 
    assign fan = fan_on ? 1 : (heater || aircon) ? 1 : 0 ;

endmodule

---

题目链接：Popcount3 - HDLBits

module top_module( 
    input [2:0] in,
    output [1:0] out );
    assign out = in[2] + in[1] + in[0] ; 
endmodule

---

题目链接：Gatesv - HDLBits

module top_module( 
    input [3:0] in,
    output reg [2:0] out_both,
    output reg [3:1] out_any,
    output reg [3:0] out_different );

    integer i ;
    always @(*) begin
        for (i = 2 ; i >= 0 ; i = i - 1) 
            out_both[i] = in[i + 1] & in[i] ; 
        for (i = 3 ; i >= 1 ; i = i - 1) 
            out_any[i] = in[i] | in[i - 1] ; 
        for (i = 2 ; i >= 0 ; i = i - 1)
            out_different[i] = in[i + 1] ^ in[i] ; 
        out_different[3] = in[3] ^ in[0] ; 
    end
	
endmodule

---

题目链接：Gatesv100 - HDLBits

module top_module( 
    input [99:0] in,
    output [98:0] out_both,
    output [99:1] out_any,
    output [99:0] out_different );

    assign out_both = in[99:1] & in[98:0] ; 
    assign out_any = in[99:1] | in[98:0] ; 
    assign out_different = in[99:0] ^ {in[0], in[99:1]} ;

endmodule