（5）HDLBits-Verilog Language-More Verilog Features

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分类专栏： HDL Bits 文章标签： fpga开发
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Conditional

一、题目要求
给定4个无符号数，求最小值。无符号数字可以与标准比较运算符(a < b)进行比较。使用条件运算符来构造双向最小值电路，然后将其中的几个组成一个4路最小值电路。你可能需要一些wire向量来表示中间结果。

二、分析
这里是要求你找出输入abcd中的最小值，并且题目已经给出题目，可以使用三目运算符，格式为

(condition ? if_true : if_false)

condition：是你设定的条件，可以是任意的布尔表达式，即结果是真或假（0或者1）
if_ture:条件为真，输出的结果，可以是任意表达式
if_false：条件为假，输出的结果，可以是任意表达式

思路如下，定义两个wire类型的变量wire1，wire2来保存两个输入之间比较的结果，，最后的输出是wire1和wire2比较的结果，注意wire1，wire2 的位宽。
代码如下

module top_module (
	input [7:0] a, b, c, d,
	output [7:0] min);//

// 	assign intermediate_result1 = compare? true: false;
 	wire [7:0] wire1,wire2;
	assign wire1=(a<b)?a:b;
	assign wire2=(c<d)?c:d;
	assign min=(wire1<wire2)?wire1:wire2;

endmodule

三、仿真图

在这里插入图片描述

Re

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IEEE Standard Verilog® Hardware Description Language
12-08
The Verilog ¤ Hardware Description Language (Verilog HDL) became an IEEE standard in 1995 as IEEE Std 1364-1995. It was designed to be simple, intuitive, and effective at multiple levels of abstraction in a standard textual format for a variety of design tools, including verification simulation, timing analysis, test analysis, and synthesis. It is because of these rich features that Verilog has been accepted to be the language of choice by an overwhelming number of IC designers.
Writing Testbenches using System Verilog
04-22
Writing Testbenches using System Verilog 英文原版的，学起来比较容易。 Writing Testbenches using System Verilog About the Cover xiii Preface xv Why This Book Is Important . . . . . . xvi What This Book Is About . . . . . . . . xvi What Prior Knowledge You Should Have . . . . . . . . xviii Reading Paths . . . xviii Why SystemVerilog? . . . . . . . . . . . . xix VHDL and Verilog . .xix Hardware Verification Languages . . . xx Code Examples . . . xxi For More Information . . . . . . . . . . xxii Acknowledgements . . . . . . . . . . . . xxii CHAPTER 1 What is Verification? 1 What is a Testbench? 1 The Importance of Verification . . . . . 2 Reconvergence Model . . . . . . . . . . . . 4 The Human Factor . 5 Automation . . . . . . . . . 6 Poka-Yoke . . . . . . . . . . 6 Table of Contents vi Writing Testbenches using SystemVerilog Redundancy . . . . . . . . . 7 What Is Being Verified? . . . . . . . . . . 7 Equivalence Checking 8 Property Checking . . . 9 Functional Verification . . . . . . . . . . . . 10 Functional Verification Approaches .11 Black-Box Verification . . . . . . . . . . . . 11 White-Box Verification . . . . . . . . . . . . 13 Grey-Box Verification . . . . . . . . . . . . 14 Testing Versus Verification . . . . . . . 15 Scan-Based Testing . 16 Design for Verification . . . . . . . . . . . . 17 Design and Verification Reuse . . . . 18 Reuse Is About Trust . 18 Verification for Reuse 19 Verification Reuse . . . 19 The Cost of Verification . . . . . . . . . 20 Summary . . . . . . . . 22 CHAPTER 2 Verification Technologies 23 Linting . . . . . . . . . 24 The Limitations of Linting Technology 25 Linting SystemVerilog Source Code . . 27 Code Reviews . . . . . . 29 Simulation . . . . . . . 29 Stimulus and Response . . . . . . . . . . . . 30 Event-Driven Simulation . . . . . . . . . . 31 Cycle-Based Simulation . . . . . . . . . . . 33 Co-Simulators . . . . . . 35 Verificatio
The Verilog Hardware Description Language.pdf
05-24
The Verilog language is a hardware description language that provides a means of specifying a digital system at a wide range of levels of abstraction. The language sup- ports the early conceptual stages of design with its behavioral level of abstraction, and the later implementation stages with its structural abstractions. The language includes hierarchical constructs, allowing the designer to control a description's complexity. Verilog was originally designed in the winter of 1983/84 as a proprietary verifica- tion/simulation product. Later, several other proprietary analysis tools were developed around the language, including a fault simulator and a timing analyzer. More recently, Verilog has also provided the input specification for logic and behavioral synthesis tools. The Verilog language has been instrumental in providing consistency across these tools. The language was originally standardized as IEEE standard #1364-1995. It has recently been revised and standardized as IEEE standard #1364-2001. This book presents this latest revision of the language, providing material for the beginning student and advanced user of the language. It is sometimes difficult to separate the language from the simulator tool because the dynamic aspects of the language are defined by the way the simulator works. Fur- ther, it is difficult to separate it from a synthesis tool because the semantics of the lan- guage become limited by what a synthesis tool allows in its input specification and produces as an implementation. Where possible, we have stayed away from simulator- and synthesis-specific details and concentrated on design specification. But, we have included enough information to be able to write working executable models. xvi The VerUog Hardware Description Language The book takes a tutorial approach to presenting the language. Indeed, we start with a tutorial introduction that presents, via examples, the major features of the lan- guage and the prevalent styles of describing systems. We follow this with a detailed presentation on using the language for synthesizing combinational and sequential sys- tems. We then continue with a more complete discussion of the language constructs. Our approach is to provide a means of learning by observing the examples and doing exercises. Numerous examples are provided to allow the reader to learn (and re- learn!) easily by example. It is strongly recommended that you try the exercises as early as possible with the aid of a Verilog simulator. The examples shown in the book are available in electronic form on the enclosed CD. Also included on the CD is a simulator. The simulator is limited in the size of description it will handle. The majority of the book assumes a knowledge of introductory logic design and sof~are programming. As such, the book is of use to practicing integrated circuit design engineers, and undergraduate and graduate electrical or computer engineering students. The tutorial introduction is organized in a manner appropriate for use with a course in introductory logic design. A separate appendix, keyed into the tutorial introduction, provides solved exercises that discuss common errors. The book has also been used for courses in introductory and upper level logic and integrated circuit design, computer architecture, and computer-aided design (CAD). It provides com- plete coverage of the language for design courses, and how a simulator works for CAD courses. For those familiar with the language, we provide a preface that covers most of the new additions to the 2001 language standard. The book is organized into eleven chapters and eight appendices. The first part of the book contains a tutorial introduction to the language which is followed by a chap- ter on its use for logic synthesis. The second part of the book, Chapters 3 through 6, provide a more rigorous presentation of the language's behavioral, hierarchical, and logic level modeling constructs. The third part of the book, Chapters 7 through 11, covers the more specialized topics of cycle-accurate modeling, timing and event driven simulation, user-defined primitives, and switch level modeling. Chapter 11 suggests two major Verilog projects for use in a university course. One appendix pro- vides tutorial discussion for beginning students. The others are reserved for the dryer topics typically found in a language manual; read those at your own risk.
[Verilog] Digital Design (Verilog): An Embedded Systems Approach Using Verilog
12-18
2007年五星书 英文版 Digital Design (Verilog): An Embedded Systems Approach Using Verilog Product Description Digital Design: An Embedded Systems Approach Using Verilog provides a foundation in digital design for students in computer engineering, electrical engineering and computer science courses. It takes an up-to-date and modern approach of presenting digital logic design as an activity in a larger systems design context. Rather than focus on aspects of digital design that have little relevance in a realistic design context, this book concentrates on modern and evolving knowledge and design skills. Hardware description language (HDL)-based design and verification is emphasized--Verilog examples are used extensively throughout. By treating digital logic as part of embedded systems design, this book provides an understanding of the hardware needed in the analysis and design of systems comprising both hardware and software components. Includes a Web site with links to vendor tools, labs and tutorials. Presents digital logic design as an activity in a larger systems design context. Features extensive use of Verilog examples to demonstrate HDL usage at the abstract behavioural level and register transfer level, as well as for low-level verification and verification environments. Includes worked examples throughout to enhance the reader's understanding and retention of the material. Companion Web site includes links to CAD tools for FPGA design from Synplicity, Mentor Graphics, and Xilinx, Verilog source code for all the examples in the book, lecture slides, laboratory projects, and solutions to exercises. Paperback: 584 pages Publisher: Morgan Kaufmann (September 14, 2007) Language: English ISBN-10: 0123695279 ISBN-13: 978-0123695277 contents c h a p t e r 1 Introduction and Methodology . . . . . . . . . . . 1 1.1 Digital Systems and Embedded Systems . . . . . . . . . . . . . . . . . 1 1.2 Binary Representation and Circuit Elements . . . . . . . . . . . . . 4 1.3 Real-World Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.1 Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3.2 Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.3.3 Static Load Levels . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.3.4 Capacitive Load and Propagation Delay . . . . . . . . . 15 1.3.5 Wire Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3.6 Sequential Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.3.7 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.3.8 Area and Packaging . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.4 Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.5 Design Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 1.5.1 Embedded Systems Design . . . . . . . . . . . . . . . . . . . 31 1.6 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.7 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 c h a p t e r 2 Combinational Basics . . . . . . . . . . . . . . . . . . 39 2.1 Boolean Functions and Boolean Algebra . . . . . . . . . . . . . . . . 39 2.1.1 Boolean Functions . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.1.2 Boolean Algebra . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.1.3 Verilog Models of Boolean Equations . . . . . . . . . . . 51 2.2 Binary Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 2.2.1 Using Vectors for Binary Codes . . . . . . . . . . . . . . . . 56 2.2.2 Bit Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 2.3 Combinational Components and Circuits . . . . . . . . . . . . . . . 62 2.3.1 Decoders and Encoders . . . . . . . . . . . . . . . . . . . . . . 62 2.3.2 Multiplexers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 2.3.3 Active-Low Logic . . . . . . . . . . . . . . . . . . . . . . . . . . 71 2.4 Verification of Combinational Circuits . . . . . . . . . . . . . . . . . . 74 2.5 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 2.6 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 c h a p t e r 3 Numeric Basics . . . . . . . . . . . . . . . . . . . . . . . 87 3.1 Unsigned Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.1.1 Coding Unsigned Integers . . . . . . . . . . . . . . . . . . . . 87 3.1.2 Operations on Unsigned Integers . . . . . . . . . . . . . . 92 3.1.3 Gray Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 3.2 Signed Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 3.2.1 Coding Signed Integers . . . . . . . . . . . . . . . . . . . . . . 119 3.2.2 Operations on Signed Integers . . . . . . . . . . . . . . . . . 122 3.3 Fixed-Point Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 3.3.1 Coding Fixed-Point Numbers . . . . . . . . . . . . . . . . . 131 3.3.2 Operations on Fixed-Point Numbers . . . . . . . . . . . . 136 3.4 Floating-Point Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 3.4.1 Coding Floating-Point Numbers . . . . . . . . . . . . . . . 138 3.5 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 3.6 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 c h a p t e r 4 Sequential Basics . . . . . . . . . . . . . . . . . . . . . . 151 4.1 Storage Elements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 4.1.1 Flip-flops and Registers . . . . . . . . . . . . . . . . . . . . . . 151 4.1.2 Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 4.1.3 Latches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 4.2 Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 4.3 Sequential Datapaths and Control . . . . . . . . . . . . . . . . . . . . . 175 4.3.1 Finite-State Machines . . . . . . . . . . . . . . . . . . . . . . . 179 4.4 Clocked Synchronous Timing Methodology . . . . . . . . . . . . . . 187 4.4.1 Asynchronous Inputs . . . . . . . . . . . . . . . . . . . . . . . . 192 4.4.2 Verification of Sequential Circuits . . . . . . . . . . . . . . 196 4.4.3 Asynchronous Timing Methodologies . . . . . . . . . . . 200 4.5 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 4.6 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 c h a p t e r 5 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 5.1 General Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 5.2 Memory Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 5.2.1 Asynchronous Static RAM . . . . . . . . . . . . . . . . . . . 220 5.2.2 Synchronous Static RAM . . . . . . . . . . . . . . . . . . . . . 222 5.2.3 Multiport Memories . . . . . . . . . . . . . . . . . . . . . . . . 229 5.2.4 Dynamic RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 5.2.5 Read-Only Memories . . . . . . . . . . . . . . . . . . . . . . . 235 5.3 Error Detection and Correction . . . . . . . . . . . . . . . . . . . . . . . 240 5.4 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 5.5 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 c h a p t e r 6 Implementation Fabrics . . . . . . . . . . . . . . . . . 249 6.1 Integrated Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 6.1.1 Integrated Circuit Manufacture . . . . . . . . . . . . . . . . 250 6.1.2 SSI and MSI Logic Families . . . . . . . . . . . . . . . . . . . 252 6.1.3 Application-Specific Integrated Circuits (ASICs) . . . 255 6.2 Programmable Logic Devices . . . . . . . . . . . . . . . . . . . . . . . . . 258 6.2.1 Programmable Array Logic . . . . . . . . . . . . . . . . . . . 258 6.2.2 Complex PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 6.2.3 Field-Programmable Gate Arrays . . . . . . . . . . . . . . 263 6.3 Packaging and Circuit Boards . . . . . . . . . . . . . . . . . . . . . . . . 269 6.4 Interconnection and Signal Integrity . . . . . . . . . . . . . . . . . . . . 272 6.4.1 Differential Signaling . . . . . . . . . . . . . . . . . . . . . . . . 276 6.5 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 6.6 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 c h a p t e r 7 Processor Basics . . . . . . . . . . . . . . . . . . . . . . 281 7.1 Embedded Computer Organization . . . . . . . . . . . . . . . . . . . . 281 7.1.1 Microcontrollers and Processor Cores . . . . . . . . . . . 283 7.2 Instructions and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 7.2.1 The Gumnut Instruction Set . . . . . . . . . . . . . . . . . . 287 7.2.2 The Gumnut Assembler . . . . . . . . . . . . . . . . . . . . . . 296 7.2.3 Instruction Encoding . . . . . . . . . . . . . . . . . . . . . . . . 298 7.2.4 Other CPU Instruction Sets . . . . . . . . . . . . . . . . . . . 300 7.3 Interfacing with Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 7.3.1 Cache Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 7.4 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 7.5 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 c h a p t e r 8 I/O Interfacing . . . . . . . . . . . . . . . . . . . . . . . 315 8.1 I/O Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 8.1.1 Input Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 8.1.2 Output Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 8.2 I/O Controllers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 8.2.1 Simple I/O Controllers . . . . . . . . . . . . . . . . . . . . . . 331 8.2.2 Autonomous I/O Controllers . . . . . . . . . . . . . . . . . 335 8.3 Parallel Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 8.3.1 Multiplexed Buses . . . . . . . . . . . . . . . . . . . . . . . . . . 338 8.3.2 Tristate Buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 8.3.3 Open-Drain Buses . . . . . . . . . . . . . . . . . . . . . . . . . . 348 8.3.4 Bus Protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 8.4 Serial Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 8.4.1 Serial Transmission Techniques . . . . . . . . . . . . . . . . 353 8.4.2 Serial Interface Standards . . . . . . . . . . . . . . . . . . . . 357 8.5 I/O Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 8.5.1 Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 8.5.2 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 8.5.3 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 8.6 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 8.7 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 c h a p t e r 9 Accelerators . . . . . . . . . . . . . . . . . . . . . . . . . 379 9.1 General Concepts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 9.2 Case Study: Video Edge-Detection . . . . . . . . . . . . . . . . . . . . . 386 9.3 Verifying an Accelerator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 9.4 Chapter Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 9.5 Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420 c h a p t e r 1 0 Design Methodology . . . . . . . . . . . . . . . . . . 423 10.1 Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 10.1.1 Architecture Exploration . . . . . . . . . . . . . . . . . . . . . 425 10.1.2 Functional Design . . . . . . . . . . . . . . . . . . . . . . . . . . 427 10.1.3 Functional Verification . . . . . . . . . . . . . . . . . . . . . . 429 10.1.4 Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 10.1.5 Physical Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 10.2 Design Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 10.2.1 Area Optimization . . . . . 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