module top_module (
input clk,
input resetn, // synchronous reset
input in,
output out);
reg o1,o2,o3;
always@(posedge clk) begin
if(~resetn) begin
out<=0;
o1<=0;
o2<=0;
o3<=0;
end
else begin
o1<=in;
o2<=o1;
o3<=o2;
out<=o3;
end
end
endmodule