Exams/review2015 fancytimer

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output [3:0] count,
    output counting,
    output done,
    input ack );
    
    parameter S0=0,S1=1,S11=2,S110=3,S1101=4,Scounter=5,Sdone=6;
    reg [2:0] state,next_state;
    reg [1:0] shift_counter;
    reg [9:0] counter1000;
    
    always@(posedge clk) begin
        if(reset)
            state<=S0;
        else
            state<=next_state;
    end
    
    //shift_counter计数 保持4个周期
    always@(posedge clk) begin
        if(state==S1101) begin
            if(shift_counter==3)
                shift_counter<=0;
        	else
            	shift_counter<=shift_counter+1'b1;
        end
        else
            shift_counter<=0;
    end
    
    //counter1000 计数1000个周期
    always@(posedge clk) begin
        if(state==Scounter)
            if(counter1000==999)
                counter1000<=0;
        	else
             	counter1000<=counter1000+1'b1;
        else
            counter1000<=0;
    end
    
    //count
    always@(posedge clk) begin
        if(state==S1101) 
            count<={count[2:0],data};
        else if((count!=0)&&(counter1000==999))
            	count<=count-1'b1;
    	else
            count<=count;
    end
    
    //Moore
    always@(*) begin
        case(state)
            S0: next_state = data?S1:S0;
            S1: next_state = data?S11:S0;
            S11: next_state = data?S11:S110;
            S110: next_state = data?S1101:S0;
            S1101: next_state = (shift_counter==3)?Scounter:S1101;
            Scounter: next_state = ((count==0)&&(counter1000==999))?Sdone:Scounter;
            Sdone: next_state = ack?S0:Sdone;
            default: next_state = S0;
        endcase
    end
 
    assign counting=(state==Scounter);
    assign done=(state==Sdone);

endmodule