[数字ic学习日记] DAY1 [verilog刷题总结] HDLBits 1-70

        鼠鼠也终于开始刷HDLBits了捏，数字漫漫长征路，迈出第一步~

        这个专题记录自己平时学习遇到的问题和不熟的知识点，方便回头复习吧（也不知道不会复习x）。

        一、Getting Started

        第一章介绍正确打开HDLBits的方法。没啥好说的。

        二、Verilog Language

        第二章有5个小节，分别是Basic，Vectors，Modules：Hierarchy，Procedures，More Verilog Features，介绍了verilog一些基本的语法和概念。

        ·BASICS

        1.verilog 中导线是定向的，信息只在一个方向流动；

        2.连续赋值语句assign

assign left_side = right_side;

        3. xorgate 异或门；xnorgate 同或门 ；norgate 或非门；

        4.模块与模块之间的连线用wire；

        ·VECTORS

        5.向量定义：

wire [99:0] my_vector;       //Declare a 100-element vector
assign out = my_vector[10];  //Part-select on bit out of the vector

        6.Concentation operator:

Concatenation needs to know the width of every component (or how would you know the length of the result?). Thus, {1, 2, 3} is illegal and results in the error message: unsized constants are not allowed in concatenations.        

The concatenation operator can be used on both the left and right sides of assignments.

input [15:0] in;
output [23:0] out;
assign {out[7:0], out[15:8]} = in;         // Swap two bytes. Right side and left side are both 16-bit vectors.
assign out[15:0] = {in[7:0], in[15:8]};    // This is the same thing.
assign out = {in[7:0], in[15:8]};       // This is different. The 16-bit vector on the right is extended to
                                        // match the 24-bit vector on the left, so out[23:16] are zero.
                                        // In the first two examples, out[23:16] are not assigned.

        7.Replication operator：

Examples:

{5{1'b1}}           // 5'b11111 (or 5'd31 or 5'h1f)
{2{a,b,c}}          // The same as {a,b,c,a,b,c}
{3'd5, {2{3'd6}}}   // 9'b101_110_110. It's a concatenation of 101 with
                    // the second vector, which is two copies of 3'b110.

       ·MODULE:HIERARCHY

        8.模块实例化

        有两种方式：

By position

The syntax to connect wires to ports by position should be familiar, as it uses a C-like syntax. When instantiating a module, ports are connected left to right according to the module's declaration. For example:

mod_a instance1 ( wa, wb, wc );

By name

Connecting signals to a module's ports by name allows wires to remain correctly connected even if the port list changes. This syntax is more verbose, however.

mod_a instance2 ( .给的(我的), .给的(我的), .给的(我的) );

·PROCEDURES 

9.always块

Since digital circuits are composed of logic gates connected with wires, any circuit can be expressed as some combination of modules and assign statements. However, sometimes this is not the most convenient way to describe the circuit. Procedures (of which always blocks are one example) provide an alternative syntax for describing circuits.

For synthesizing hardware, two types of always blocks are relevant:

Combinational: always @(*)

Clocked: always @(posedge clk)

Combinational always blocks are equivalent to assign statements, thus there is always a way to express a combinational circuit both ways. The choice between which to use is mainly an issue of which syntax is more convenient. The syntax for code inside a procedural block is different from code that is outside. Procedural blocks have a richer set of statements (e.g., if-then, case), cannot contain continuous assignments, but also introduces many new non-intuitive ways of making errors. 

        这里hdlbits讲的比较浅，过几天看看夏宇闻关于这部分的内容再完善一下。

10.赋值

There are three types of assignments in Verilog:

• Continuous assignments (assign x = y;). Can only be used when not inside a procedure ("always block").
• Procedural blocking assignment: (x = y;). Can only be used inside a procedure.
• Procedural non-blocking assignment: (x <= y;). Can only be used inside a procedure.

        连续赋值（assign x=y）除过程块内都可使用，过程块内可以使用阻塞赋值和非阻塞赋值，在组合逻辑always块内使用阻塞赋值，时序逻辑always块内使用非阻塞赋值。

        ！！记得总结阻塞赋值和非阻塞赋值