Writing Testbenches

Tb/clock

`timescale 1ps/1ps
module top_module ;
    
    reg clk;
    
    dut dut ( .clk(clk) ) ;
    
    initial begin
       clk <= 0; 
    end
    
    always #5 clk <= ~clk;
    //#5ps clk翻转一次，周期10 ps；
    
endmodule

Tb/tb1

`timescale 1ps/1ps
module top_module (output reg A, output reg B);//

    // generate input patterns here
    initial begin
        A <= 0; B <= 0;
		#10 A <= 1; //10ps后A为1；
        #5 B <= 1; //5ps后B为1；
        #5 A <=0; //5ps后A为0；
        #20 B <= 0; //20ps后B为0；
    end

endmodule

Tb/and

module top_module;
    
    reg [1:0] in;
    wire out;
    
    initial begin
       	in <= 2'b0;
		#10		in <= 2'b01;
		#10		in <= 2'b10;
		#10		in <= 2'b11;
    end
    
    andgate andgate (.in(in),.out(out));

endmodule

Tb/tb2

module top_module;
    reg clk,in;
    reg [2:0] s;
    wire out;
    
    q7 q7 (.clk(clk),.in(in),.s(s),.out(out));
    
    initial begin
    	clk<=0;in<=0;s<=2;
    	#10 s<=6;
        #10 s<=2;in<=1;
        #10 s<=7;in<=0;
        #10 s<=0;in<=1;
        #30 in<=0;
    end
    
    always #5 clk<=~clk;

endmodule

Tb/tff

module top_module;
    reg clk,reset,t;
    wire q;
    
    tff tff (.clk(clk),.reset(reset),.t(t),.q(q));
    
    initial begin
        clk<=0;reset<=0;t<=0;
        #10 reset<=1;t<=1;
        #10 reset<=1;t<=0;
        #10 reset<=0;t<=1;
        #10 reset<=0;t<=0; //测试所有可能情况；
    end
             
    always #5 clk<=~clk;
             
endmodule