`timescale 1ps/1ps
module top_module (output reg A, output reg B);//
// generate input patterns here
initial begin
A <= 0; B <= 0;
#10 A <= 1; //10ps后A为1;
#5 B <= 1; //5ps后B为1;
#5 A <=0; //5ps后A为0;
#20 B <= 0; //20ps后B为0;
end
endmodule
module top_module;
reg [1:0] in;
wire out;
initial begin
in <= 2'b0;
#10 in <= 2'b01;
#10 in <= 2'b10;
#10 in <= 2'b11;
end
andgate andgate (.in(in),.out(out));
endmodule