Building Larger Circuits

Exams/review2015 shiftcount

module top_module (
    input clk,
    input shift_ena,
    input count_ena,
    input data,
    output [3:0] q);
    
    always@(posedge clk)begin
        if(shift_ena)begin
            q[3:0]<={q[2:0],data};	
            //q=0000,shift_ena=1,data=1;
            //q=0001,shift_ena=1,data=0;
            //q=0010,shift_ena=1,data=0;
            //q=0100,shift_ena=1,data=1;
            //q=1001,shift_ena=0,data=0;
        end
        if(count_ena)begin
            q<=q-4'b1;
        end
    end

endmodule

Exams/review2015 fsmseq

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output start_shifting);
    
    reg[3:0] data_buf;	//定义一个保存四位data的寄存器，用以寻找1101；
    
    always@(posedge clk)begin
        data_buf<={data_buf[2:0],data}; //移位寄存器，将data的数据移入data_buf；
        if(reset)begin
            start_shifting<=0;
            data_buf<=0;
        end
        else begin
            if({data_buf[2:0],data}==4'b1101)begin
                //此处如果用data_buf判断，会导致start_shifting延后一个时钟，即{data_buf[2:0],data}赋值给data_buf的一个时钟。
                start_shifting<=1'b1;
            end
        end
    end

endmodule

Exams/review2015 fsmshift

module top_module (
    input clk,
    input reset,      // Synchronous reset
    output shift_ena);
    
    reg[1:0] cont;	//计算周期数；
    
    always@(posedge clk)begin
        cont<=2'd0;
        if(reset)begin
            shift_ena<=1;
        end
        else begin
            cont<=cont+1'd1;	//延时四个周期；
            if(cont==2'd3)begin
                shift_ena<=0;
            end
        end
    end

endmodule

Exams/review2015 fsm

module top_module (
    input clk,
    input reset,      // Synchronous reset
    input data,
    output shift_ena,
    output counting,
    input done_counting,
    output done,
    input ack );
    
    parameter A=0,B=1,C=2,D=3,E=4,F=5,G=6;
    //A:data[0],B:data[1],C:data[2],D:data[3],E:shift_ena,F:done_counting,G:ack
    
    reg[3:0] state,next_state;
    reg[1:0] count;
       
    always@(posedge clk)begin
        if(reset)begin
            state<=A;
            count<=2'd0;
        end
        else begin
            state<=next_state;
            if(state==E)begin
                if(count==2'd3)begin
                	count<=0; 
                    shift_ena<=1;
                end
                else begin
                    count <=count+1'b1;
                end
            end
        end
    end
    
    always@(*)begin
        case(state)
            A:next_state = (data)?B:A;//1
            B:next_state = (data)?C:A;//1
            C:next_state = (~data)?D:C;//0
            D:next_state = (data)?E:A;//1
            E:next_state = (count==2'd3)?F:E;
            F:next_state = (done_counting)?G:F;
            G:next_state = (ack)?A:G;
        endcase
    end
    
    
    
    
    assign counting = (state==F)?1:0;
    assign done =(state==G)?1:0;
 
endmodule