Fsm1
法一:
module top_module(
input clk,
input areset, // Asynchronous reset to state B
input in,
output out);//
parameter A=0, B=1;
reg state, next_state;
always @(*) begin // This is a combinational always block
// State transition logic
case(state)
A:begin next_state=in?A:B; end
B:begin next_state=in?B:A; end
endcase
end
always @(posedge clk, posedge areset) begin // This is a sequential always block
// State flip-flops with asynchronous reset
if(areset)begin
state<=B;
end
else begin
state<=next_state;
end
end
assign out=state;
// Output logic
// assign out = (state == ...);
endmodule
法二:
module top_module(
input clk,
input areset, // Asynchronous reset to state B
input in,
output out);//
parameter A=0, B=1;
reg state;
always @(posedge clk, posedge areset) begin // This is a sequential always block
// State flip-flops with asynchronous reset
if(areset)begin
state<=B;
end
else begin
case(state)
A:begin state<=in?A:B; end
B:begin state<=in?B:A; end
endcase
end
end
assign out=state;
// Output logic
// assign out = (state == ...);
endmodule
Fsm1s
module top_module(
input clk,
input reset, // Asynchronous reset to state B
input in,
output out);//
parameter A=0, B=1;
reg state;
always @(posedge clk) begin // This is a sequential always block
// State flip-flops with asynchronous reset
if(reset)begin
state<=B;
end
else begin
case(state)
A:begin state<=in?A:B; end
B:begin state<=in?B:A; end
endcase
end
end
assign out=state;
// Output logic
// assign out = (state == ...);
endmodule
Fsm3comb
module top_module(
input in,
input [1:0] state,
output [1:0] next_state,
output out); //
parameter A=0, B=1, C=2, D=3;
// State transition logic: next_state = f(state, in)
always@(*)begin
case(state)
A:begin next_state=in?B:A; end
B:begin next_state=in?B:C; end
C:begin next_state=in?D:A; end
D:begin next_state=in?B:C; end
endcase
end
// Output logic: out = f(state) for a Moore state machine
assign out=(state==D)?1'b1:1'b0;
endmodule
Fsm3onehot
module top_module(
input in,
input [3:0] state,
output [3:0] next_state,
output out); //
parameter A=0, B=1, C=2, D=3;
// State transition logic: Derive an equation for each state flip-flop.
assign next_state[A] = state[A] & (~in) | state[C] & (~in);
assign next_state[B] = state[A] & in | state[B] & in | state[D] & in;
assign next_state[C] = state[B] & (~in) | state[D] & (~in);
assign next_state[D] = state[C] & in;
// Output logic:
assign out = state[D];
endmodule
Fsm3
module top_module(
input clk,
input in,
input areset,
output out); //
parameter A=0,B=1,C=2,D=3;
reg[1:0] state,next_s;
// State transition logic
always@(*)begin
case(state)
A:begin next_s=in?B:A; end
B:begin next_s=in?B:C; end
C:begin next_s=in?D:A; end
D:begin next_s=in?B:C; end
endcase
end
// State flip-flops with asynchronous reset
always@(posedge clk or posedge areset)begin
if(areset)begin
state<=A;
end
else begin
state<=next_s;
end
end
// Output logic
assign out=(state==D)?1:0;
endmodule
Lemmings1
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
output walk_left,
output walk_right); //
parameter LEFT=0, RIGHT=1;
reg state, next_state;
always @(*) begin
// State transition logic
case(state)
LEFT:
begin
if(bump_left)begin
next_state<=RIGHT;
end
else begin
next_state<=LEFT;
end
end
RIGHT:
begin
if(bump_right)begin
next_state<=LEFT;
end
else begin
next_state<=RIGHT;
end
end
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if(areset)begin
state<=LEFT;
end
else begin
state<=next_state;
end
end
// Output logic
assign walk_left = (state == LEFT);
assign walk_right = (state == RIGHT);
endmodule
Lemmings2
以下代码仿真成功
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah );
parameter LEFT=0, RIGHT=1, fall_l=2, fall_r=3;
reg[1:0] state, next_state;//共四个state,要定义位宽;
reg[2:0] out;//{walk_left, walk_right, aaah}
always @(*) begin
// State transition logic
case(state)
LEFT: begin next_state = ground ? (bump_left ? RIGHT : LEFT) : fall_l; end
RIGHT: begin next_state = ground ? (bump_right ? LEFT : RIGHT) : fall_r; end
fall_l: begin next_state = ground ? LEFT : fall_l; end
fall_r: begin next_state = ground ? RIGHT : fall_r; end
endcase
end
always @(posedge clk or posedge areset) begin
// State flip-flops with asynchronous reset
if(areset)begin
state <= LEFT;
end
else begin
state <= next_state;
end
end
always @(posedge clk or posedge areset) begin
// State flip-flops with asynchronous reset
if(areset)begin
out<=3'b100;
end
else begin
case(next_state)
LEFT: begin out <= 3'b100; end //有方向,不叫
RIGHT: begin out <= 3'b010; end //有方向,不叫
fall_l: begin out <= 3'b001; end //没有方向,叫
fall_r: begin out <= 3'b001; end //没有方向,叫
endcase
end
end
// Output logic
assign {walk_left, walk_right, aaah} = out;
endmodule
以下代码仿真失败,时序有问题
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
output walk_left,
output walk_right,
output aaah );
parameter LEFT=0, RIGHT=1;
reg state, next_state;
always @(*) begin
// State transition logic
case(state)
LEFT:
begin
if(ground==0)begin
aaah<=1;
next_state<=0;
end
else begin
aaah=0;
if(bump_left)begin
next_state<=RIGHT;
end
else begin
next_state<=LEFT;
end
end
end
RIGHT:
begin
if(ground==0)begin
aaah<=1;
next_state<=0;
end
else begin
aaah<=0;
if(bump_right)begin
next_state<=LEFT;
end
else begin
next_state<=RIGHT;
end
end
end
endcase
end
always @(posedge clk, posedge areset) begin
// State flip-flops with asynchronous reset
if(areset)begin
state<=LEFT;
end
else begin
state<=next_state;
end
end
// Output logic
assign walk_left = (state == LEFT && ground);
assign walk_right = (state == RIGHT && ground);
endmodule
Lemmings3
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging );
parameter LEFT=0, RIGHT=1, fall_l=2, fall_r=3, dig_l=4, dig_r=5;
reg[3:0] state, next_state;
reg[3:0] out;//{walk_left, walk_right, aaah, digging}
always@(*)begin
case(state)
LEFT:
begin
if(ground && ~dig && bump_left)begin
next_state = RIGHT;
end
if(ground && ~dig && ~bump_left)begin
next_state = LEFT;
end
if(~ground)begin
next_state = fall_l;
end
if(ground && dig)begin
next_state = dig_l;
end
end
RIGHT:
begin
if(ground && ~dig && bump_right)begin
next_state = LEFT;
end
if(ground && ~dig && ~bump_right)begin
next_state = RIGHT;
end
if(~ground)begin
next_state = fall_r;
end
if(ground && dig)begin
next_state = dig_r;
end
end
fall_l:
begin
if(~ground)begin
next_state = fall_l;
end
if(ground && ~bump_right)begin
next_state = LEFT;
end
end
fall_r:
begin
if(~ground)begin
next_state = fall_r;
end
if(ground && ~bump_right)begin
next_state = RIGHT;
end
end
dig_l:
begin
if(~ground)begin
next_state = fall_l;
end
else begin
next_state = dig_l;
end
end
dig_r:
begin
if(~ground)begin
next_state = fall_r;
end
else begin
next_state = dig_r;
end
end
endcase
end
always @(posedge clk or posedge areset) begin
// State flip-flops with asynchronous reset
if(areset)begin
state <= LEFT;
end
else begin
state <= next_state;
end
end
//{walk_left, walk_right, aaah, digging}
always@(posedge clk or posedge areset)begin
if(areset)begin
out <= 4'b1000;
end
else begin
case(next_state)
LEFT: begin out <= 4'b1000; end
RIGHT: begin out <= 4'b0100; end
fall_l: begin out <= 4'b0010; end
fall_r: begin out <= 4'b0010; end
dig_l: begin out <= 4'b0001; end
dig_r: begin out <= 4'b0001; end
endcase
end
end
assign {walk_left, walk_right, aaah, digging} = out;
endmodule
Lemmings4
自己写出来总有不对的地方,参考这篇后终于成功,看来多信号还是分开写比较好。
module top_module(
input clk,
input areset, // Freshly brainwashed Lemmings walk left.
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging );
parameter LEFT=0, RIGHT=1, fall_l=2, fall_r=3, dig_l=4, dig_r=5, splatter=6;
reg[3:0] state, next_state;
reg[4:0] con;//计算20内的落地时间;
reg timeout;
//状态机
always@(*) begin
case(state)
LEFT: begin next_state = ground ? ( dig ? dig_l : (bump_left ? RIGHT : LEFT) ) : fall_l; end
RIGHT: begin next_state = ground ? ( dig ? dig_r : (bump_right ? LEFT : RIGHT) ) : fall_r; end
fall_l: begin next_state = ground ? ( timeout ? splatter : LEFT ) : fall_l; end
fall_r: begin next_state = ground ? ( timeout ? splatter : RIGHT ) : fall_r; end
dig_l: begin next_state = ground ? dig_l : fall_l; end
dig_r: begin next_state = ground ? dig_r : fall_r; end
splatter: begin next_state = splatter; end
endcase
end
//state赋值
always @(posedge clk or posedge areset) begin
// State flip-flops with asynchronous reset
if(areset)begin
state <= LEFT;
end
else begin
state <= next_state;
end
end
//timeout
always@(posedge clk or posedge areset)begin
if(areset)begin
timeout <= 0;
end
else if(con == 5'd20)begin
timeout <= 1;
end
else begin
timeout <= timeout;
end
end
//con
always@(posedge clk or posedge areset)begin
if(areset)begin
con <= 5'd0;
end
else if(next_state==fall_l || next_state==fall_r)begin
con <= con + 1'b1;
end
else begin
con <= 5'd0;
end
end
assign walk_left = (state == LEFT);
assign walk_right = (state == RIGHT);
assign aaah = ((state == fall_l) || (state == fall_r));
assign digging = ((state == dig_l) || (state == dig_r));
endmodule
Fsm onehot
这题按要求只能参考Fsm3onehot
module top_module(
input in,
input [9:0] state,
output [9:0] next_state,
output out1,
output out2);
assign next_state[0] = ~in & (state[0] | state[1] | state[2] | state[3] | state[4] | state[7] | state[8] | state[9] ) ;
assign next_state[1] = in & (state[0] | state[8] | state[9] ) ;
assign next_state[2] = in & state[1] ;
assign next_state[3] = in & state[2] ;
assign next_state[4] = in & state[3] ;
assign next_state[5] = in & state[4] ;
assign next_state[6] = in & state[5] ;
assign next_state[7] = in & (state[6] | state[7]) ;
assign next_state[8] = ~in & state[5] ;
assign next_state[9] = ~in & state[6] ;
assign out1 = state[8] | state[9];
assign out2 = state[7] | state[9];
endmodule