Build a circuit from a simulation waveform

Sim/circuit2

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//
	
    //q = a'b'c'd'+a'b'cd+a'bc'd+a'bcd'+ab'c'd+ab'cd'+abc'd'+abcd;公式化简法
    //q = (a^b) & (c^d) + ~(a^b) & ~(c^d); 令A=(a^b),B=(c^d)，还能化简
    //q = ~((a^b)^(c^d))
    
    assign q = (a^b) & (c^d) | ~(a^b) & ~(c^d); // Fix me

endmodule

Sim/circuit3

module top_module (
    input a,
    input b,
    input c,
    input d,
    output q );//
    
	//写出特征方程，然后公式化简法化简
    assign q = (a|b) & (c^d|c); // Fix me
    //卡诺图化简
    //assign q = a&d | a&c | b&d | b&c;

endmodule

Sim/circuit8

module top_module (
    input clock,
    input a,
    output p,
    output q );
    
    always@(*)begin
        if(clock)begin
        	p = a;
    	end
        else begin
        	p = p; 
        end
    end
    
    always@(negedge clock)begin
        q <= p; 
    end

endmodule

Sim/circuit9

module top_module (
    input clk,
    input a,
    output [3:0] q );
    
    always@(posedge clk)begin
        if(a)begin
            q <= 4'd4;
        end
        else begin
            if(q==4'd6)begin
                q <= 4'd0;
            end
            else begin
                q <= q+1'b1;
            end
        end
    end

endmodule

Sim/circuit10

module top_module (
    input clk,
    input a,
    input b,
    output q,
    output state  );
    
    always@(posedge clk)begin
        if(a && b)begin 
            //60-70,a=b=1,70往后state=1；
            //70-80，a=b=0，80往后state=0；
            //80-90，a=b=1,state=1，90往后state=1；
            //130-140，a=b=0,140往后state=0；
            state <= 1'b1;
        end
        if(~a && ~b)begin
            state <= 1'b0;
        end
    end
    //state=1，a b同或；state=0，a b异或；
    assign q = state?(~(a^b)):(a^b);

endmodule