时序问题求助

求助：以下问题仿真结果为什么所有信号都提前一个clock，怎么才能让时序正常

Lemmings2

 我的写法如下：

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah ); 
    
    parameter LEFT=0, RIGHT=1;
    reg state, next_state;

    always @(*) begin
        // State transition logic
        case(state)
            LEFT: 
                begin
                    if(ground==0)begin
                        aaah<=1;
                        next_state<=0;
                    end
                    else begin
                        aaah=0;
                        if(bump_left)begin
                        	next_state<=RIGHT;
                    	end
                    	else begin
                        	next_state<=LEFT;
                    	end
                    end
                end
            RIGHT:
                begin
                    if(ground==0)begin
                        aaah<=1;
                        next_state<=0;
                    end
                    else begin
                        aaah<=0;
                        if(bump_right)begin
                        	next_state<=LEFT;
                    	end
                    	else begin
                        	next_state<=RIGHT;
                    	end
                    end
                end
        endcase
    end

    always @(posedge clk, posedge areset) begin
        // State flip-flops with asynchronous reset
        if(areset)begin
            state<=LEFT;
        end
        else begin
            state<=next_state;
        end
    end

    // Output logic
    assign walk_left = (state == LEFT && ground);
    assign walk_right = (state == RIGHT && ground);

endmodule

仿真结果如下：