FPGA项目集合汇总

说明

        练习1是实现1-0转换状态机器，练习2是实现输入输出计数器的实现，练习3是与门的实现。

练习4是当时钟每经历10次高电平，则翻转电平。

练习1

test1代码

module Moore(
    input 	clk,	//????
    input 	areset,  //??????????
    input 	in	,//????
    output 	reg[1:0] out //????
);
//------------<???????>------------------------------------------
//???????????
parameter 	A=2'b01; 
parameter	B=2'b10; 
//------------<reg??>-------------------------------------------------	
reg	[1:0]	cur_state;	//???????
reg	[1:0]	next_state;     //???????

always @(posedge clk or posedge areset) begin    
if(areset)
	cur_state <= B;	//???????
else 
	cur_state <= next_state;	//????????
end
always @(*) begin
	if(areset)
	next_state = B;	//???????
	else
case(cur_state)	//?????????
A:	
if(!in)	
next_state = B;	//??????
else
next_state = A;	//???????
B:	
if(!in)
	next_state = A;	//??????
	else
	next_state = B;	//???????				
default:;
	endcase
end
always @(posedge clk or posedge areset) begin    
    if(areset)
	out <= 1'b1;//??????
else 
case(next_state)//???????????????????
A:	out <= 1'b0;
B:	out <= 1'b1;
default:out <= 1'b1;
  endcase
end
endmodule

test_top文件

`timescale 10ns / 10ns
module moore_tb;  
    reg clk; 
    reg areset; 
    reg in;  
    wire out;  
    Moore u_Moore(
    .clk(clk),
    .areset(areset),
    .in(in),
    .out(out)
    );
initial
begin
  in=1;
  clk=0; 
  areset=1;
  #200 areset=0;
end
always #10 clk=~clk;

always#10  in=~in;

endmodule

练习2

test代码

module counter (
  input wire clk,
  input wire clr,
  input wire b,
  output reg [7:0] a
);

  // ??????
  always @(posedge clk or posedge clr) begin
    if (clr)
      a <= 8'b0;
    else if (b)
      a <= a + 1'b1;

     if(a==8'b00001000)
      begin
	a<=8'b0;
      end
  end

endmodule

test_top文件

module counter_t;
  reg clk;
  reg clr;
  reg b;
  wire [7:0] a;

  counter uut (.clk(clk), .clr(clr), .b(b), .a(a));

  // ????
  always begin
    #5 clk = ~clk;
  end

  // ???
  initial begin
    clk = 0;
    clr = 1;
    b = 0;
    #10 clr = 0;


    // ??b?1?a?1
    #10 b = 1;

    // ??b?0????
    #10 b = 0;

    // ??b?1?a?1
    #10 b = 1;

    // ??b?0????
    #10 b = 0;

    // ??b?1?a?1
    #10 b = 1;

    // ??b?0????
    #10 b = 0;//4
    // ??b?1?a?1
    #10 b = 1;

    // ??b?0????
    #10 b = 0;

    // ??b?1?a?1
    #10 b = 1;

    // ??b?0????
    #10 b = 0;

    // ??b?1?a?1
    #10 b = 1;

    // ??b?0????
    #10 b = 0;//8
    // ??b?1?a?1
    #10 b = 1;

    // ??b?0????
    #10 b = 0;//9
    // ??b?1?a?1
    #10 b = 1;

    // ??b?0????
    #10 b = 0;//10
    // ??b?1?a?1
    #10 b = 1;

    // ??b?0????
    #10 b = 0;


  end
 

endmodule

练习3

test代码

module logic_circuit (
  input wire clk,
  input wire rest,
  input wire A,
  input wire B,
  output reg C
);

  // ??????
  always @(posedge clk or posedge rest) begin
    if (rest)
      C <= 1'b0;
    else begin
      case ({A, B})
        2'b11: C <= 1'b1;
        2'b00: C <= 1'b0;
        2'b01: C <= 1'b0;
        2'b10: C <= 1'b0;
      endcase
    end
  end

endmodule

test_top

module logic_circuit_tb;
  reg clk;
  reg rest;
  reg A;
  reg B;
  wire C;

  logic_circuit uut (.clk(clk), .rest(rest), .A(A), .B(B), .C(C));

  // ????
  always begin
    #5 clk = ~clk;
  end

  // ???
  initial begin
    clk = 0;
    rest = 1;
    A = 0;
    B = 0;
    #10 rest = 0;
    
        // A=1, B=1, C=1
    #50 A = 1; B = 1;

    // A=0, B=0, C=0
    #50 A = 0; B = 0;

    // A=0, B=1, C=0
    #50 A = 0; B = 1;

    // A=1, B=0, C=0
    #50 A = 1; B = 0;
  end



endmodule

练习4

test代码

module circuit_module (
  input wire clk,
  input wire rest_n,
  output reg C =1'b0
);

  reg [3:0] count=4'b0000;

  // ??????
  always @(posedge clk or negedge rest_n) begin
    if (!rest_n)
      C <= 1'b0;
    else begin
      if (count == 4'b1001) begin
        C <= ~C;
        count <= 4'b0;
      end else
        count <= count + 1'b1;
    end
  end

endmodule

test_top

module circuit_tb;
  reg clk;
  reg rest_n;
  wire C;

  circuit_module uut (.clk(clk), .rest_n(rest_n), .C(C));



  // ???
  initial begin
    clk = 0;
    rest_n = 1;
    #10 rest_n = 1;

    
  end

  // ????
  always begin
    #5 clk = ~clk;
  end

endmodule