四位全加器

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最新推荐文章于 2024-07-23 15:08:44 发布

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文章标签： java java

本文链接：https://blog.csdn.net/m0_71138074/article/details/125202294

版权

这篇博客展示了如何使用Verilog编写一个4位加法器模块adder4，并提供了对应的测试用例test_adder4。测试用例详细说明了输入变量的变化及对应的输出结果，通过$monitor显示即时状态，并使用$dumpfile保存仿真波形。

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rtl视图

代码

module adder4(cout,sum,ina,inb,cin);
output[3:0] sum;
output cout;
input[3:0] ina,inb;
input cin;

assign {cout,sum}=ina+inb+cin;
endmodule

tset代码

/*
File Name : test_adder4.v
Description : The testbench of the adder_4.v
Written By : LiMing
Data : 2011/04/18 20:13

modefied : 在仿真的时候，把延时从10ns改为5ns
： cout显示为2位
*/

//test_adder4 (top-level module)
`timescale 1ns/1ns
module test_adder4;

//Declare variables
wire[3:0] sum;
wire cout;
reg[3:0] ina,inb;
reg cin;

//Instantiate the module adder4
adder4 adder4_1(cout,sum,ina,inb,cin);

//Stimulate the inputs, Finish the stimulation at 90 time units
initial
begin
#0 ina = 4'b0001; inb = 4'b1010; cin = 1'b0;
#5 ina = 4'b0010; inb = 4'b1010; cin = 1'b1;
#5 ina = 4'b0010; inb = 4'b1110; cin = 1'b0;
#5 ina = 4'b0011; inb = 4'b1100; cin = 1'b1;
#5 ina = 4'b0111; inb = 4'b1001; cin = 1'b0;
#5 ina = 4'b0001; inb = 4'b1100; cin = 1'b1;
#5 ina = 4'b0011; inb = 4'b1100; cin = 1'b0;
#5 ina = 4'b0111; inb = 4'b1111; cin = 1'b1;
#5 $finish;
end

initial
$monitor("At time %t, ina(%b) + inb(%b) + cin(%b) = sum(%b)(%2d),cout(%b)",$time, ina, inb, cin, sum, sum, cout);