VCS 生成代码覆盖率

Step 1. Compile the source files

vcs -Mupdate -cm line    +v2k    -sverilog  source.v   tb_source.sv

The db/verilog directory contains data files written by VCS about the design such as cm.format_info, cm.map_info, cm.mod_info, and cm.src_info.
The coverage/verilog directory is initially empty, but during simulation VCS writes intermediate data files (also called test files) in this directory. cmView reads these files.
The reports directory where cmView writes its report files.

Step 2. Run the simulation and monitor for coverage

simv -cm line

注意：第二步完成后仿真进入命令行模式：ucli%。这时要输入exit命令，退出ucli%模式。若按ctr+c强制退出，则不能生成