verilog 四位全加器

行为级建模

module adder4_1(     //串行
a,b,cin,sum
); 
input  [3:0]a,b;
input  cin;
output  [3:0]sum;

assign sum=a+b+cin;

endmodule

仿真

module sim1();
    reg [3:0] a,b;
    reg cin;
    wire [3:0]sum;
    
    initial 
    begin
       #10 a=4'h0001;b=4'h0001;cin=1;
       #10 a=4'h0010;b=4'h0010;cin=1;
       #10 a=4'h0110;b=4'h0110;cin=0;
       #10 a=4'h1111;b=4'h0111;cin=1;
    end
  adder4_1 utt1(.a(a),.b(b),.cin(cin),.sum(sum));
endmodule