verilog 4位全加器的实现

4位全加器

module ad4 (cout,sum,ina,inb,cin);
  input  [3:0] ina,inb;
  input cin;
  output [3:0] sum;
  output cout;

  assign {cout,sum} = ina + inb + cin;
  endmodule

`timescale 1ns/1ps 
module tb ()
 reg [3:0] ina,inb;
 reg cin;
 wire [3:0] sum;
 wire cout;
  
 integer i,j;
 always #5 cin = ~cin;
 initial 
 begin  
          ina = 0;
          inb = 0;
          cin = 0;
          for (i = 1; i<16;i=i+1)
          #10 ina = i;
 end 
  initial 
  begin 
          for (j=1;j<16;j=j+1)
          #10 inb = j;
   end 
   initial 
   begin 
           $monitor($time,,,"%d + %d  +%b = {%b,%d}",ina,inb,cin,cout,sum);
           #200;
           $finish;
   end 
//print waneform 
initial begin 
$fsdbDumpfile ("ad4,fsdb);
$fsdbDumpvars(0,tb);
end 

ad4 dut (
                .ina (ina),
                .inb (inb),
                .sum (sum),
                .cin (cin),
                .cout (cout)
                );
 endmodule