牛客刷题＜13＞优先编码器电路

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已于 2022-08-21 17:04:36 修改

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分类专栏： FPGA 文章标签： fpga开发

于 2022-08-21 16:54:21 首次发布

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题目：优先编码器电路①_牛客题霸_牛客网

知识：此题主要是学会一个新知识点,case,casex,casez区别

解法一：此代码是casez，不是case

`timescale 1ns/1ns
module encoder_0(
    input [8:0] I_n,
    output reg [3:0] Y_n
);
    always@(*)begin
        casez(I_n)
            9'b111111111: Y_n = 4'b1111;
            9'b0????????: Y_n = 4'b0110;
            9'b10???????: Y_n = 4'b0111;
            9'b110??????: Y_n = 4'b1000;
            9'b1110?????: Y_n = 4'b1001;
            9'b11110????: Y_n = 4'b1010;
            9'b111110???: Y_n = 4'b1011;
            9'b1111110??: Y_n = 4'b1100;
            9'b11111110?: Y_n = 4'b1101;
            9'b111111110: Y_n = 4'b1110;
            default: Y_n = 4'b0000;
        endcase
    end
endmodule

解法二：常规解法

`timescale 1ns/1ns

module encoder_0(
   input      [8:0]         I_n   ,
   
   output reg [3:0]         Y_n   
);
    always@(*)begin
        if(I_n[8]==0)begin
            Y_n[3] = 0;
            Y_n[2] = 1;
            Y_n[1] = 1;
            Y_n[0] = 0;
        end
        else if(I_n[7]==0)begin
            Y_n[3] = 0;
            Y_n[2] = 1;
            Y_n[1] = 1;
            Y_n[0] = 1;
        end
        else if(I_n[6]==0)begin
            Y_n[3] = 1;
            Y_n[2] = 0;
            Y_n[1] = 0;
            Y_n[0] = 0;
        end
        else if(I_n[5]==0)begin
            Y_n[3] = 1;
            Y_n[2] = 0;
            Y_n[1] = 0;
            Y_n[0] = 1;
        end
        else if(I_n[4]==0)begin
            Y_n[3] = 1;
            Y_n[2] = 0;
            Y_n[1] = 1;
            Y_n[0] = 0;
        end
        else if(I_n[3]==0)begin
            Y_n[3] = 1;
            Y_n[2] = 0;
            Y_n[1] = 1;
            Y_n[0] = 1;
        end
        else if(I_n[2]==0)begin
            Y_n[3] = 1;
            Y_n[2] = 1;
            Y_n[1] = 0;
            Y_n[0] = 0;
        end
        else if(I_n[1]==0)begin
            Y_n[3] = 1;
            Y_n[2] = 1;
            Y_n[1] = 0;
            Y_n[0] = 1;
        end
        else if(I_n[0]==0)begin
            Y_n[3] = 1;
            Y_n[2] = 1;
            Y_n[1] = 1;
            Y_n[0] = 0;
        end
        else begin
            Y_n[3] = 1;
            Y_n[2] = 1;
            Y_n[1] = 1;
            Y_n[0] = 1;
        end
            
    end
endmodule

解法三:casex

`timescale 1ns/1ns
module encoder_0(
   input      [8:0]         I_n   ,
   
   output reg [3:0]         Y_n   
);

always @(*)begin
   casex(I_n)
      9'b111111111 : Y_n = 4'b1111;
      9'b0xxxxxxxx : Y_n = 4'b0110;
      9'b10xxxxxxx : Y_n = 4'b0111;
      9'b110xxxxxx : Y_n = 4'b1000;
      9'b1110xxxxx : Y_n = 4'b1001;
      9'b11110xxxx : Y_n = 4'b1010;
      9'b111110xxx : Y_n = 4'b1011;
      9'b1111110xx : Y_n = 4'b1100;
      9'b11111110x : Y_n = 4'b1101;
      9'b111111110 : Y_n = 4'b1110;
      default      : Y_n = 4'b1111;
   endcase    
end 
     
endmodule