牛客刷题＜18＞3-8译码器

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已于 2022-08-23 22:11:30 修改

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分类专栏： FPGA 文章标签： fpga开发

于 2022-08-23 22:07:02 首次发布

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题目：实现3-8译码器①_牛客题霸_牛客网

知识点：Verilog中and or not的用法

在程序模块中出现的and，or和not都是Verilog语言的保留字，由Verilog语言的原语

规定了它们的接口顺序和用法，分别表示与门，或门，非门

例：

module muxtwo（out,a,b,sl）;

input a,b,sl;

output out;

not u1(nsl,sl); //将sl进行非运算，nsl为sl非运算后的值，u1相当于逻辑元件非门

and #1 u2（sela，a，nsl）; //将a和nsl进行与运算，sela为与运算后的输出值，u2相当于逻辑元件与门

and #1 u3（selb，b，sl）；//将b和sl进行与运算

or #1 u4(out,sela,selb); //将sela和selb进行或运算

/*#1表示输入到输出延迟1个单位时间*/

endmodule

解法一

`timescale 1ns/1ns

module decoder_38(
   input             E1_n   ,
   input             E2_n   ,
   input             E3     ,
   input             A0     ,
   input             A1     ,
   input             A2     ,
   
   output wire       Y0_n   ,  
   output wire       Y1_n   , 
   output wire       Y2_n   , 
   output wire       Y3_n   , 
   output wire       Y4_n   , 
   output wire       Y5_n   , 
   output wire       Y6_n   , 
   output wire       Y7_n   
);
    
    not NO0 (A00,A0),
    NO1(A10,A1),
    NO2(A20,A2),
    NO0_N(Y0_n,Y0),
    NO1_N(Y1_n,Y1),
    NO2_N(Y2_n,Y2),
    NO3_N(Y3_n,Y3),
    NO4_N(Y4_n,Y4),
    NO5_N(Y5_n,Y5),
    NO6_N(Y6_n,Y6),
    NO7_N(Y7_n,Y7),
    NOE1(E1,E1_n),
    NOE2(E2,E2_n),
    NOE3(E3,E3_n);
    
    and AND0(Y0,A00,A10,A20,E3,E2,E1),
    AND1(Y1,A0,A10,A20,E3,E2,E1),
    AND2(Y2,A00,A1,A20,E3,E2,E1),
    AND3(Y3,A0,A1,A20,E3,E2,E1),
    AND4(Y4,A00,A10,A2,E3,E2,E1),
    AND5(Y5,A0,A10,A2,E3,E2,E1),
    AND6(Y6,A00,A1,A2,E3,E2,E1),
    AND7(Y7,A0,A1,A2,E3,E2,E1);

endmodule

解法二

`timescale 1ns/1ns

module decoder_38(
   input             E1_n   ,
   input             E2_n   ,
   input             E3     ,
   input             A0     ,
   input             A1     ,
   input             A2     ,
   
   output wire       Y0_n   ,  
   output wire       Y1_n   , 
   output wire       Y2_n   , 
   output wire       Y3_n   , 
   output wire       Y4_n   , 
   output wire       Y5_n   , 
   output wire       Y6_n   , 
   output wire       Y7_n   
);
    
    assign Y0_n = ~(({A2,A1,A0}==3'd0)&&({E3,E2_n,E1_n} ==3'b100));
    assign Y1_n = ~(({A2,A1,A0}==3'd1)&&({E3,E2_n,E1_n} ==3'b100));
    assign Y2_n = ~(({A2,A1,A0}==3'd2)&&({E3,E2_n,E1_n} ==3'b100));
    assign Y3_n = ~(({A2,A1,A0}==3'd3)&&({E3,E2_n,E1_n} ==3'b100));
    assign Y4_n = ~(({A2,A1,A0}==3'd4)&&({E3,E2_n,E1_n} ==3'b100));
    assign Y5_n = ~(({A2,A1,A0}==3'd5)&&({E3,E2_n,E1_n} ==3'b100));
    assign Y6_n = ~(({A2,A1,A0}==3'd6)&&({E3,E2_n,E1_n} ==3'b100));
    assign Y7_n = ~(({A2,A1,A0}==3'd7)&&({E3,E2_n,E1_n} ==3'b100));

endmodule

解法三

`timescale 1ns/1ns

module decoder_38(
   input             E1_n   ,
   input             E2_n   ,
   input             E3     ,
   input             A0     ,
   input             A1     ,
   input             A2     ,
   
   output wire       Y0_n   ,  
   output wire       Y1_n   , 
   output wire       Y2_n   , 
   output wire       Y3_n   , 
   output wire       Y4_n   , 
   output wire       Y5_n   , 
   output wire       Y6_n   , 
   output wire       Y7_n   
);
    
    assign Y0_n = ~E3 | E2_n | E1_n | A2 | A1 | A0;
    assign Y1_n = ~E3 | E2_n | E1_n | A2 | A1 | ~A0;
    assign Y2_n = ~E3 | E2_n | E1_n | A2 | ~A1 | A0;
    assign Y3_n = ~E3 | E2_n | E1_n | A2 | ~A1 | ~A0;
    assign Y4_n = ~E3 | E2_n | E1_n | ~A2 | A1 | A0;
    assign Y5_n = ~E3 | E2_n | E1_n | ~A2 | A1 | ~A0;
    assign Y6_n = ~E3 | E2_n | E1_n | ~A2 | ~A1 | A0;
    assign Y7_n = ~E3 | E2_n | E1_n | ~A2 | ~A1 | ~A0;
    
endmodule

解法四

`timescale 1ns/1ns

module decoder_38(
   input             E1_n   ,
   input             E2_n   ,
   input             E3     ,
   input             A0     ,
   input             A1     ,
   input             A2     ,
   
   output wire       Y0_n   ,  
   output wire       Y1_n   , 
   output wire       Y2_n   , 
   output wire       Y3_n   , 
   output wire       Y4_n   , 
   output wire       Y5_n   , 
   output wire       Y6_n   , 
   output wire       Y7_n   
);
    wire  E;
    assign E = E3 & ~E2_n & ~E1_n;
    assign Y0_n = ~(E & ~A2 & ~A1 & ~A0);
    assign Y1_n = ~(E & ~A2 & ~A1 &  A0);
    assign Y2_n = ~(E & ~A2 &  A1 & ~A0);
    assign Y3_n = ~(E & ~A2 &  A1 &  A0);
    assign Y4_n = ~(E &  A2 & ~A1 & ~A0);
    assign Y5_n = ~(E &  A2 & ~A1 &  A0);
    assign Y6_n = ~(E &  A2 &  A1 & ~A0);
    assign Y7_n = ~(E &  A2 &  A1 &  A0);
    
endmodule

解法五：自己写的

`timescale 1ns/1ns

module decoder_38(
   input             E1_n   ,
   input             E2_n   ,
   input             E3     ,
   input             A0     ,
   input             A1     ,
   input             A2     ,
   
   output wire       Y0_n   ,  
   output wire       Y1_n   , 
   output wire       Y2_n   , 
   output wire       Y3_n   , 
   output wire       Y4_n   , 
   output wire       Y5_n   , 
   output wire       Y6_n   , 
   output wire       Y7_n   
);
    reg Y0n;
    reg Y1n;
    reg Y2n;
    reg Y3n;
    reg Y4n;
    reg Y5n;
    reg Y6n;
    reg Y7n;
    always@(*)begin
        if(E3==0|E2_n==1|E1_n==1)begin
            Y0n  = 1'b1;
            Y1n  = 1'b1;
            Y2n  = 1'b1;
            Y3n  = 1'b1;
            Y4n  = 1'b1;
            Y5n  = 1'b1;
            Y6n  = 1'b1;
            Y7n  = 1'b1;
        end
        else begin
            case({A2,A1,A0})
                3'b000:begin
                   Y0n = 1'b0; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; 
                   Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1; 
                end
                3'b001:begin
                   Y0n = 1'b1; Y1n = 1'b0; Y2n = 1'b1; Y3n = 1'b1; 
                   Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1; 
                end
                3'b010:begin
                   Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b0; Y3n = 1'b1; 
                   Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1; 
                end
                3'b011:begin
                   Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b0; 
                   Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1; 
                end
                3'b100:begin
                   Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; 
                   Y4n = 1'b0; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1; 
                end
                3'b101:begin
                   Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; 
                   Y4n = 1'b1; Y5n = 1'b0; Y6n = 1'b1; Y7n = 1'b1; 
                end
                3'b110:begin
                   Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; 
                   Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b0; Y7n = 1'b1; 
                end
                3'b111:begin
                   Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; 
                   Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b0; 
                end
                default:begin
                   Y0n = 1'b1; Y1n = 1'b1; Y2n = 1'b1; Y3n = 1'b1; 
                   Y4n = 1'b1; Y5n = 1'b1; Y6n = 1'b1; Y7n = 1'b1;  
                end
            endcase
        end
            
    end
    assign  Y0_n = Y0n;
    assign  Y1_n = Y1n;
    assign  Y2_n = Y2n;
    assign  Y3_n = Y3n;
    assign  Y4_n = Y4n;
    assign  Y5_n = Y5n;
    assign  Y6_n = Y6n;
    assign  Y7_n = Y7n;
    
endmodule

Testbench

`timescale 1ns/1ns

module testbench();
    wire E1_n;
    wire E2_n;
    wire E3;
    wire A0;
    wire A1;
    wire A2;
    wire Y0_n;
    wire Y1_n;
    wire Y2_n;
    wire Y3_n;
    wire Y4_n;
    wire Y5_n;
    wire Y6_n;
    wire Y7_n;
    initial begin
        $dumpfile("out.vcd");
        $dumpvars(0,testbench);
    end
    decoder_38 inst(
        .E1_n(E1_n),
        .E2_n(E2_n),
        .E3(E3),
        .A0(A0),
        .A1(A1),
        .A2(A2),
        .Y0_n(Y0_n),
        .Y1_n(Y1_n),
        .Y2_n(Y2_n),
        .Y3_n(Y3_n),
        .Y4_n(Y4_n),
        .Y5_n(Y5_n),
        .Y6_n(Y6_n),
        .Y7_n(Y7_n)
    );
endmodule