牛客刷题＜28＞输入序列不连续的序列检测

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最新推荐文章于 2024-06-17 16:38:27 发布

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题目：输入序列不连续的序列检测_牛客题霸_牛客网

解法一：状态机容易理解

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
    reg [3:0] pstate,nstate;
    parameter idle = 4'd0,
    s1_d0=4'd1,
    s2_d01=4'd2,
    s3_d011= 4'd3,
    s4_d0110= 4'd4;
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)
            pstate<= idle;
        else
            pstate<= nstate;
    end
    always@(*)begin
        case(pstate)
            idle:
                if(data_valid&&!data)
                    nstate=s1_d0;
                else
                    nstate=idle;
            s1_d0:
                if(data_valid)begin
                    if(data_valid)begin
                        if(data) nstate=s2_d01;
                        else nstate=s1_d0;
                    end
                end
            s2_d01:
                if(data_valid)begin
                    if(data) nstate=s3_d011;
                    else nstate = s2_d01;
                end
                else nstate = s2_d01;
            s3_d011:
                if(data_valid)begin
                    if(!data) nstate=s4_d0110;
                    else nstate = idle;
                end
                else nstate = s3_d011;
            s4_d0110:
                if(data_valid)begin
                    if(!data) nstate = s1_d0;
                    else nstate = idle;
                end
                else nstate = idle;
            default: nstate = idle;
        endcase
    end
    always@(pstate or rst_n)begin
        if(!rst_n==1)
            match=1'b0;
        else if(pstate==s4_d0110)
            match=1'b1;
        else
            match = 1'b0;
    end
endmodule

解法二：简易版

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
    reg [3:0] sr;
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)
            sr <= 4'd0;
        else if(data_valid)
            sr <= {sr[2:0],data};
    end
   
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n) 
            match <= 4'd0;
        else if(data_valid && sr[2:0] == 3'b011 && !data)
            match <= 1'b1;
        else
            match <= 1'b0;
    end
   
endmodule

解法三

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
    reg [3:0] temp;
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)
            temp <= 4'b0;
        else if(data_valid)begin
            temp <= {temp[2:0],data};
        end
    end
    always@(temp or data_valid)begin
        if(temp == 4'b0110&data_valid)
            match =1;
        else
            match =0;
    end
endmodule

解法四

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
    parameter idle=3'd0,s0 =3'd1,s1=3'd2,s2=3'd3,s3=3'd4;
    reg [2:0] c_state,n_state;
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)
            c_state <= idle;
        else
            c_state <= n_state;
    end
    always@(*)begin
        case(c_state)
            idle: n_state=data_valid?(~data?s0:idle):idle;
            s0: n_state=data_valid?(data?s1:s0):s0;
            s1: n_state=data_valid?(data?s2:s0):s1;
            s2: n_state=data_valid?(data?idle:s3):s2;
            s3: n_state=data_valid?(data?s1:s0):idle;
            default: n_state=idle;
        endcase
    end
    always@(posedge clk or negedge rst_n)begin
        if(!rst_n)
            match <= 0;
        else if(n_state==s3)
            match <= 1;
        else
            match <= 0;
    end
endmodule