1. Combination Circuit 1
module top_module (
input a,
input b,
output q );//
assign q = a & b; // Fix me
endmodule
2. Combination Circuit 2
module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q = (~a&~b&~c&~d)|(~a&~b&c&d)|(~a&b&~c&d)|(~a&b&c&~d)|
(a&b&~c&~d)|(a&b&c&d)|(a&~b&~c&d)|(a&~b&c&~d);
endmodule
3.Combination Circuit 3
module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q = (b&d)|(b&c)|(a&d)|(a&c); // Fix me
endmodule
4. Combination Circuit 4
module top_module (
input a,
input b,
input c,
input d,
output q );//
assign q = c|(b&~c); // Fix me
endmodule
5. Circuits 5
module top_module (
input [3:0] a,
input [3:0] b,
input [3:0] c,
input [3:0] d,
input [3:0] e,
output [3:0] q );
parameter s0 = 4'b0000;
parameter s1 = 4'b0001;
parameter s2 = 4'b0010;
parameter s3 = 4'b0011;
reg[3:0] qt;
always@(*)
begin
case(c)
s0: qt = b;
s1: qt = e;
s2: qt = a;
s3: qt = d;
default : qt = 4'b1111;
endcase
end
assign q = qt;
endmodule
6. Combination Circuit 6
module top_module (
input [2:0] a,
output [15:0] q );
reg [15:0] qt;
always@(*)
begin
case(a)
3'b000: qt = 16'h1232;
3'b001: qt = 16'haee0;
3'b010: qt = 16'h27d4;
3'b011: qt = 16'h5a0e;
3'b100: qt = 16'h2066;
3'b101: qt = 16'h64ce;
3'b110: qt = 16'hc526;
3'b111: qt = 16'h2f19;
endcase
end
assign q = qt;
endmodule